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DS1877 Datasheet(PDF) 42 Page - Maxim Integrated Products

Part # DS1877
Description  SFP Controller for Dual Rx Interface
PDF  65 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS1877 Datasheet(HTML) 42 Page - Maxim Integrated Products

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Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
Table 01h, Register FBh: ALARM EN0
Table 01h, Register FCh: WARN EN3
POWER-ON VALUE
00h
READ ACCESS
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS
PW2 or (PW1 and RWTBL1C)
A2h AND B2h MEMORY
Different A2h and B2h memory locations
MEMORY TYPE
Nonvolatile (SEE)
FBh
LOS HI
LOS LO
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BIT 7
BIT 0
Layout is identical to ALARM0 in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 88h) determines
whether this memory exists in Table 01h or 05h.
BIT 7
LOS HI: Enables alarm to create FLTINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS HI alarm.
1 = Enables interrupt from LOS HI alarm.
BIT 6
LOS LO: Enables alarm to create FLTINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS LO alarm.
1 = Enables interrupt from LOS LO alarm.
BITS 5:0
RESERVED
POWER-ON VALUE
00h
READ ACCESS
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS
PW2 or (PW1 and RWTBL1C)
A2h AND B2h MEMORY
Common A2h and B2h memory locations
MEMORY TYPE
Nonvolatile (SEE)
FCh
TEMP HI
TEMP LO
VCC HI
VCC LO
RESERVED
RESERVED
RESERVED
RESERVED
BIT 7
BIT 0
Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create FLTINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.
BIT 7
TEMP HI [A2h or B2h]:
0 = Disables interrupt from the TEMP HI warning.
1 = Enables interrupt from the TEMP HI warning.
BIT 6
TEMP LO [A2h or B2h]:
0 = Disables interrupt from the TEMP LO warning.
1 = Enables interrupt from the TEMP LO warning.
BIT 5
VCC HI [A2h or B2h]:
0 = Disables interrupt from the VCC HI warning.
1 = Enables interrupt from the VCC HI warning.
BIT 4
VCC LO [A2h or B2h]:
0 = Disables interrupt from the VCC LO warning.
1 = Enables interrupt from the VCC LO warning.
BITS 3:0
RESERVED



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