LTC4261 datasheet(34/74 Pages) AD

34 / 74 page

LTC4283

Rev. B

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APPLICATIONS INFORMATION

inverted or non-inverted external fault (see External Fault

and Auto-Retry). When configured as general purpose

outputs, the output data for PGIO1–PGIO4 and ADIO1–

ADIO4 are stored in bits[7:4] in PGIO_CONFIG_2 register

0x11 and bits[3:0] in ADC_CONFIG register 0x12, respec-

tively. When selected, ADIO1–ADIO4 are also monitored

by the on-board ADC (see Data Converters).

If the PGIO2_ACLB bit in CONTROL_1 register 0x0A is

set, PGIO2 is configured as an inverted indicator of active

current limit after startup. During startup PGIO2 is held

low. After the internal power good signal is latched, if the

OC_STATUS bit in FAULT_STATUS register 0x03 is 0,

PGIO2 goes high impedance. If the OC_STATUS bit is set

to indicate that active current limit is engaged, PGIO2 is

pulled low.

Regardless of the configurations, PGIO1–PGIO4 and

ADIO1–ADIO4 all have comparators monitoring the volt-

age on these pins with a threshold of 1.28V. The results

are stored in INPUT_STATUS register 0x02.

Design Examples

Example 1: Design Procedure for Systems with Large

Input Steps

Consider a battery operated system with maximum load

power of 600W, a supply voltage range of –36V to –72V

(–36V to –72V input step is allowed), and a load capaci-

tance of CL = 500µF as shown in Figure 2.

The maximum load current is calculated as

IL(MAX) =

PL(MAX)

VS(MIN)

600W

36V

= 16.7A

Step 1. Configure current limit and select current sense

resistor. Since a –36V to –72V input step is a valid operat-

ing condition, the current limit should be twice the maxi-

mum load current to minimize the temperature rise in the

MOSFET following a large input step:

ILIM = 2 • IL(MAX) = 33.3A

With a constant power load, when the load voltage ramps

from 36V to 72V following the input step, the load cur-

rent is halved. The LPFB (load power foldback) bit in

CONFIG_1 register 0x0D is set to 1 so that the current

limit will be maintained at approximately twice the load

current during the output ramp.

Sense resistor is selected assuming they will carry the

maximum current, or 33.3A in this example. Selection is

a matter of total cost, sense voltage (configurable from

15mV to 30mV in 1mV steps), allowable dissipation, avail-

ability of discrete resistance values, using multiple devices

to reduce the sensing errors associated with high current

density at the interface between the PCB and resistor, and

using multiple devices to ballast current flow across a

wide path, between 2 or more connectors, or between

2 or more MOSFET. These factors are iterated until an

acceptable solution is found. First, determine the num-

ber of resistors needed to handle the total sense power.

Compute the total sense power starting with the minimum

sense voltage or 15mV:

PS = VILIM(MIN) • ILIM = 15mV • 33.3A = 500mW

Second, compute the number of resistors needed to

handle this power. For example, 1206 resistors are rated

for 250mW dissipation. A conservative design is half as

much, or 125mW.

NRS =

125mW

500mW

125mW

= 4

Thus at least four parallel 1206 resistors are needed for

each channel. Third, compute the resistance value:

RS=

VILIM

ILIM

= 15mV

33.3A

=450µΩ

Four resistors of 1.8mΩ each would give the correct

sense resistance. Fourth, use the closest next-larger avail-

able sense resistor value and adjust the sense voltage as

needed to restore the current. In this case, a 2mΩ sense

resistor value is selected and the sense voltage is adjusted

to 16mV. Recompute the numbers:

RS =

2mΩ

= 500µΩ

ILIM =

16mV

500µΩ

= 32A

PS = 16mV • 32A = 512mW

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