LTC4261 datasheet(22/74 Pages) AD

22 / 74 page

LTC4283

Rev. B

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APPLICATIONS INFORMATION

Inrush Control

Inrush current control can be configured in two ways.

First, if the DVDT bit in CONTROL_1 register 0x0A is set

to 1, the inrush current is controlled in dV/dt mode by

an external capacitor connected between RAMP and VEE

(the RAMP capacitor, CR), as shown in Figure 6. In dV/dt

mode, the inrush current is limited by controlling a con-

stant output voltage ramp rate (dV/dt). During startup,

when the GATE voltage reaches the MOSFET threshold

voltage, RAMP outputs a fixed 2.5μA current to charge

CR while the inrush current charges load capacitor CL.

During dV/dt control the LTC4283 regulates the RAMP

to the attenuated load voltage between RTNS and DRNS

with an offset:

VRAMP = VRTNS – VDRNS + 0.18V

and regulates the inrush current to a fixed value that is a

function of the attenuation ratio, r and the ratio between

load capacitance and RAMP capacitance:

IINRUSH = 2.5µA •r •

The attenuation ratio r is set by the external resistive divid-

ers at RTNS (RRT and RRB) and DRNS (RDT and RDB) in

Figure 6:

RRT+RRB

RRB

RDT+RDB

RDB

RTNS and DRNS represent the attenuated input voltage

and MOSFET drain voltage, respectively. The differential

Figure 5. LTC4283 Turn-On Sequence

–48V

INPUT

UVLO AND UV CLEARED

128ms

GATE

VIN – 1.8V

4283 F05

CURRENT

PGIO1

PWRGD1#

READY

PWRGD2#

READY

INTERNAL

POWER

GOOD

INRUSH

(LATCHED)

LOAD1

LOAD1 + LOAD2

MOSFET

VDS

2.048V

PGIO2

PGIO3

FAULTY POWER GOOD INPUT

NORMAL POWER GOOD INPUT

256ms

512ms

256ms

Figure 6. dV/dt Inrush Control Using RAMP Capacitor

RIN

CIN

RRT

200k

RRB

5.11k

RDT

200k

RDB

5.11k

–48V

RTN

–48V

INPUT

VEE

SENSE– SENSE+

GATE

VZ VIN

RTNS

LTC4283

VEE

RAMP

VLOAD

VOUT

DRNS

–

4283 F06

VEE

LTC4261 Datasheet(PDF) 22 Page - Analog Devices

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