LTC4261 datasheet(23/74 Pages) AD

23 / 74 page

LTC4283

Rev. B

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APPLICATIONS INFORMATION

voltage between RTNS and DRNS therefore represents

the attenuated load voltage. The operation range of VRTNS,

VDRNS and VRTNS – VDRNS is from 0V to 2.8V.

The dV/dt control is only active during initial startup.

After the turn-on sequence is completed and power good

signals are activated, the dV/dt inrush control mode is

disabled and RAMP is discharged with a 4mA current.

RAMP will also be discharged under any GATE turn-off

conditions. In the dV/dt mode the inrush current must be

set lower than the folded back current limit level to avoid

triggering the current limit (see below).

The second inrush control mechanism is active cur-

rent limiting. This is enabled by clearing the DVDT bit in

CONTROL_1 register 0x0A. In this mode the inrush cur-

rent is regulated to the folded back current limit:

IINRUSH = ILIM • aSTARTUP

where ILIM is the current limit and aSTARTUP is the startup

foldback factor. ILIM is determined by the current limit

sense voltage VILIM and the sense resistance RS.

ILIM=

VILIM

VILIM is configurable from 15mV to 30mV in 1mV steps.

aSTARTUP is configurable to 10%, 20%, 50% and 100%

(no foldback) of current limit. During startup the current

limit foldback profile is flat and does not change with

output voltage. See Current Limit Adjustment and Current

Limit Foldback for details. In this mode the RAMP capaci-

tor CR at the RAMP pin no longer takes effect. If CR is

omitted, RAMP must be left open.

Power Good Monitors and PGI Fault

After the MOSFET is turned on, the following conditions

must be met before the power good signals are activated.

First, the DRAIN voltage must fall below 2.048V to indicate

the MOSFET drain is low. Second, RTNS − DRNS must be

higher than the external threshold voltage at VOUTTH to

indicate the output voltage is high. Last, GATE voltage must

satisfy the GATE high (>VIN – 1.8V) condition. When all

three conditions are met, an internal power good signal is

latched, the PG_STATUS bit in SYSTEM_STATUS register

0x00 is set, and a series of three delay cycles are started

as illustrated in Figure 5. When the first delay of 256ms

expires, the first power good signal PGIO1 turns on the

first load. When the second delay of 256ms expires, the

second power good signal PGIO2 can be used to turn on

a second load.

Following the two 256ms delays, a third delay of 512ms is

started for monitoring PGIO3 as a power good input (PGI)

watchdog. Before this delay expires, PGIO3 must be pulled

low or high (polarity configurable by register 0x10) by an

external supply monitor to indicate the load is working prop-

erly. Otherwise, the MOSFET is turned off and a PGI fault is

logged in FAULT register 0x04. The MOSFET is allowed to

auto-retry after a delay of 128ms following the PGI fault if

the PGI_RETRY bit in CONTROL_2 register 0x0B is set to

1. Both power good signals and the power good input can

be configured into inverted or non-inverted polarity using

PGIO_CONFIG_1 register 0x10 (see Table 12). To disable

the PGI watchdog, connect PGIO3 to VEE or INTVCC depend-

ing on the configured polarity, or configure PGIO3 as gen-

eral purpose input or output using register 0x10.

Power good signals are reset in two configurable ways.

If the PWRGD_RESET_CNTRL bit in CONTROL_1 reg-

ister 0x0A is set to 1, power good signals are reset by

an output low condition as indicated by RTNS − DRNS

< VOUTTH. In Figure 2a VOUTTH is biased at 0.8V, so

power good signals will be reset when RTNS – DRNS

drops below 0.8V, which corresponds to VOUT < 32V. If

the PWRGD_RESET_CNTRL bit is cleared, power good

signals are reset by any GATE turn-off conditions except

overvoltage fault. When the power good signals are reset,

the power good delays and the PGI delay are also reset.

Turn-Off Sequence

In any of the following conditions, the MOSFET is turned

off by pulling down the GATE pin with 18mA current

source and the FET_ON_STATUS bit in SYSTEM_STATUS

1. VIN is lower than 7.6V (VIN undervoltage lockout).

2. INTVCC is lower than 3.8V (INTVCC undervoltage

lockout).

3. EN# is high.

4. ON bit in CONTROL_1 register 0x0A is cleared.

LTC4261 Datasheet(PDF) 23 Page - Analog Devices

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