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DLPA2000 Datasheet(PDF) 29 Page - Texas Instruments |
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DLPA2000 Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 39 page ![]() 9 Power Supply Recommendations The following power supplies are all required to operate the DMD: • VSS • VBIAS • VDD • VDDI • VOFFSET • VRESET DMD power-up and power-down sequencing is strictly controlled by the DLPAxxxx device. CAUTION For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to any of the prescribed power-up and power-down requirements may affect device reliability. See the DMD power supply sequencing requirements in Figure 9-1. VBIAS, VDD, VDDI, VOFFSET, and VRESET power supplies must be coordinated during power-up and power-down operations. Failure to meet any of the below requirements significantly reduces DMD reliability and lifetime. Common ground VSS must also be connected. 9.1 DMD Power Supply Power-Up Procedure • During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD. • During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4. Refer to Table 9-1 for power-up delay requirements. • During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET. • Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Section 9.3. • During power-up, LPSDR input pins must not be driven high until after VDD /VDDI have settled at operating voltages listed in Section 6.4. 9.2 DMD Power Supply Power-Down Procedure • Power-down sequence is the reverse order of the previous power-up sequence. During power-down, VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground. • During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4. • During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET. • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Section 9.3. • During power-down, LPSDR input pins must be less than VDD /VDDI specified in Section 6.4. www.ti.com DLP300S DLPS214A – JULY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DLP300S |
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