Table 5-1. Pin Functions – Connector Pins(1) (continued)

PIN

TYPE

SIGNAL

DATA RATE

DESCRIPTION

PACKAGE NET

LENGTH(2) (mm)

NAME

NO.

VOFFSET

D1

Power

Supply voltage for HVCMOS core

logic. Supply voltage for stepped

high level at micromirror address

electrodes.

Supply voltage for offset level at

micromirrors.

VOFFSET

D17

Power

VRESET

B1

Power

Supply voltage for negative reset level

at micromirrors.

VRESET

B18

Power

VDD

B6

Power

VDD

B10

Power

VDD

B19

Power

VDD

C6

Power

Supply voltage for LVCMOS core logic.

Supply voltage for LPSDR inputs.

Supply voltage for normal high level at

micromirror address electrodes.

VDD

C10

Power

VDD

C19

Power

VDD

D2

Power

VDD

D18

Power

VDD

D19

Power

VDDI

B2

Power

Supply voltage for SubLVDS receivers.

VDDI

C2

Power

VDDI

C3

Power

VDDI

D3

Power

VSS

B3

Ground

Common return.

Ground for all power.

VSS

B4

Ground

VSS

B8

Ground

VSS

B12

Ground

VSS

B13

Ground

VSS

B14

Ground

VSS

B15

Ground

VSS

B16

Ground

VSS

B17

Ground

VSS

C4

Ground

VSS

C8

Ground

VSS

C16

Ground

VSS

C17

Ground

VSS

D14

Ground

VSS

D15

Ground

VSS

D16

Ground

(1)

Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

(2)

Net trace lengths inside the package:

Relative dielectric constant for the FQK ceramic package is 9.8.

Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.

Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.

(3)

The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

DLP300S

DLPS214A – JULY 2021 – REVISED AUGUST 2021

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