6.7 Timing Requirements (continued)

Device electrical characteristics are over Section 6.4 unless otherwise noted.

MIN

NOM

MAX

UNIT

Rise slew rate

20% to 80% reference points, Figure

6-5

0.7

1

V/ns

Fall slew rate

80% to 20% reference points, Figure

6-5

0.7

1

V/ns

Cycle time DCLK,

Figure 6-7

1.79

1.85

ns

Pulse duration DCLK high

50% to 50% reference points, Figure

6-7

0.79

ns

Pulse duration DCLK low

50% to 50% reference points, Figure

6-7

0.79

ns

Setup time

D(0:3) valid before

DCLK ↑ or DCLK ↓, Figure 6-7

Hold time

D(0:3) valid after

DCLK ↑ or DCLK ↓, Figure 6-7

Window time

Setup time + Hold time, Figure 6-7,

Figure 6-8

0.3

ns

ENABLE+REFGEN

Power-up receiver(3)

2000

ns

(1)

Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.

(2)

Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-4.

(3)

Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

(4)

Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

LS_CLK

50%

LS_WDATA

50%

Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B,

Low Power Double Data Rate (LPDDR) JESD209B.

Figure 6-2. LPSDR Switching Parameters

LS_CLK and LS_WDATA

80

20

70

30

Time

100

Figure 6-3. LPSDR Input Slew Rate

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DLP300S

DLPS214A – JULY 2021 – REVISED AUGUST 2021

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