6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)(10)

PARAMETER

TEST CONDITIONS(2)

MIN

TYP

MAX

UNIT

LPSDR INPUT(7)

DC input high voltage(9)

0.7 × VDD

VDD + 0.3

V

DC input low voltage(9)

–0.3

0.3 × VDD

V

AC input high voltage(9)

0.8 × VDD

VDD + 0.3

V

AC input low voltage(9)

–0.3

0.2 × VDD

V

Figure 6-12

0.1 × VDD

0.4 × VDD

V

Low–level input current

–100

nA

High–level input current

100

nA

LPSDR OUTPUT(8)

DC output high voltage

0.8 × VDD

V

DC output low voltage

0.2 × VDD

V

CAPACITANCE

Input capacitance LPSDR

ƒ = 1 MHz

10

pF

Input capacitance SubLVDS

ƒ = 1 MHz

10

pF

Output capacitance

ƒ = 1 MHz

10

pF

(1)

The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

(2)

All voltage values are with respect to the ground pins (VSS).

(3)

To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(4)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(5)

Supply power dissipation based on non–compressed commands and data.

(6)

Supply power dissipation based on 3 global resets in 200 µs.

(7)

LPSDR specifications are for pins LS_CLK and LS_WDATA.

(8)

LPSDR specification is for pin LS_RDATA.

(9)

Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) Device electrical characteristics are over Section 6.4 unless otherwise noted.

6.7 Timing Requirements

Device electrical characteristics are over Section 6.4 unless otherwise noted.

MIN

NOM

MAX

UNIT

LPSDR

Rise slew rate(1)

(30% to 80%) × VDD, Figure 6-3

1

3

V/ns

Fall slew rate(1)

(70% to 20%) × VDD, Figure 6-3

1

3

V/ns

Rise slew rate(2)

(20% to 80%) × VDD, Figure 6-4

0.25

V/ns

Fall slew rate(2)

(80% to 20%) × VDD, Figure 6-4

0.25

V/ns

Cycle time LS_CLK,

Figure 6-2

7.7

8.3

ns

Pulse duration LS_CLK high

50% to 50% reference points, Figure

6-2

3.1

ns

Pulse duration LS_CLK low

50% to 50% reference points, Figure

6-2

3.1

ns

Setup time

LS_WDATA valid before LS_CLK ↑,

Figure 6-2

1.5

ns

Hold time

LS_WDATA valid after LS_CLK ↑,

Figure 6-2

1.5

ns

Window time(1) (4)

Setup time + Hold time, Figure 6-2

3

ns

Window time derating(1) (4)

For each 0.25 V/ns reduction in slew

rate below 1 V/ns, Figure 6-6

0.35

ns

SubLVDS

DLP300S

DLPS214A – JULY 2021 – REVISED AUGUST 2021

www.ti.com

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