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ES9038Q2M Datasheet(PDF) 18 Page - ESS Technology,Inc |
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ES9038Q2M Datasheet(HTML) 18 Page - ESS Technology,Inc |
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18 / 65 page ![]() CONFIDENTIAL Rev. 1.3 July 17, 2019 ES9038Q2M Datasheet ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643- 8800 • Fax (408) 643-8801 18 Register 3: SPDIF Configuration Bits [7:4] [3] [2] [1] [0] Mnemonic reserved spdif_user_bits spdif_ig_data spdif_ig_valid reserved Default 4’d4 1’b0 1’b0 1’b0 1’b0 Bit Mnemonic Description [7:4] reserved [3] spdif_user_bits Both SPDIF channel status bits and SPDIF user bits are available for readback via the I2C interface. To reduce register count the channel status bits and user bits occupy the same register space. Setting user_bits will present the SPDIF user bits on the read-only register interface instead of the default channel status bits. • 1’b1: presents the SPDIF user bits on the read-only register interface • 1’b0: presents the SPDIF channel status bits on the read-only register interface (default) [2] spdif_ig_data Configures the SPDIF decoder to ignore the ‘data’ flag in the channel status bits. • 1’b1: ignore the data flag in the channel status bits and continue to process the decoded SPDIF data • 1’b0: mute the SPDIF data when the data flag is set (default) Note: Enabling the SPDIF output when data is present could cause undesirable noise if the SPDIF data is compressed audio or a non - standard format. [1] spdif_ig_valid Configures the SPDIF decoder to ignor e the ‘valid’ flag in the SPDIF stream. • 1’b1: ignore the valid flag and continue to process the decoded SPDIF data • 1’b0: mute the SPDIF data when the valid flag is invalid (default) [0] reserved |
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