ES9038Q2M datasheet(11/65 Pages) ESS

11 / 65 page

July 17, 2019

CONFIDENTIAL Rev. 1.3

ES9038Q2M Datasheet

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-

8800 • Fax (408) 643-8801

THD Compensation

THD Compensation can be used to minimize distortion from external PCB components and layout through the generation of

inverse second and third harmonic components matching the target system distortion profile.

THD compensation can be enabled via thd_enb in Register 13: THD Bypass.

The coefficient for manipulating second harmonic distortion is stored in Register 22-23: THD Compensation C2.

The coefficient for manipulating third harmonic distortion is stored in Register 24-25: THD Compensation C3.

All channels use the same compensation coefficients.

Standby Mode

For lowest power consumption, the following should be performed to enter the stand-by mode:

•

RESETB pin should be brought to low digital level to:

Shut off the DACs, Oscillator and internal regulator.

Force digital I/O pins (DATA_CLK, DATA1, GPIO1, GPIO2, SDA ) into tri-state mode

•

If XI is supplied externally, it should be stopped at a logic low level

To resume from standby mode bring RESETB to high digital level, resume XI if supplied externally, and reinitialize all

registers.

DVDD Supply

The ES9038Q2M is equipped with a regulated DVDD supply powered from DVCC. The internal DVDD regulator must be

decoupled to DGND with a capacitor that maintains a minimum value of 1

F at 1.2V over the target operating temperature

range. The recommended capacitor for decoupling DVDD is a 4.7

F ±20%, X5R 6.3V 0402.

Headphone Amp Control (when used with SABRE9602)

When used with the SABRE9602 headphone amp, the following pins can be used to provide dedicated control.

ES9038

Connect to

SABRE9602 pin

ES9038 Reset State

ES9038 Normal Operation

HPSDb

AMP_PDB

HPSDb is pulled down via internal

100kΩ

resistor on HPSDb

HPSDb is controlled via amp_pdb and amp_pdb_ss

in Register 39: General Configuration 2

SW_CTRL

SW is controlled by GPIO2 via internal

120kΩ resistor to select AUX (GPIO2=1) or

standby (GPIO2=0) mode

SW is controlled via sw_ctrl_en[1] once sw_ctrl_en[0]

is programmed to be 1’b1 in Register 39: General

Configuration 2.

FSYNC

Tri-stated

Sets charge pump frequency via Register 30-31:

Charge Pump Clock

BIAS

1’b0

General purpose output controlled via bias_ctrl in

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