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ES9038Q2M Datasheet(PDF) 43 Page - ESS Technology,Inc |
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ES9038Q2M Datasheet(HTML) 43 Page - ESS Technology,Inc |
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43 / 65 page ![]() July 17, 2019 CONFIDENTIAL Rev. 1.3 ES9038Q2M Datasheet 43 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643- 8800 • Fax (408) 643-8801 Register 65 (Read-Only): GPIO Readback Bits [7:2] [1] [0] Mnemonic reserved gpio2 gpio1 Default 6’d0 1’b0 1’b0 Bit Mnemonic Description 7:2] reserved Hard coded to 6’d0. [1] gpio2 Contains the state of the GPIO2 pin. [0] gpio1 Contains the state of the GPIO1 pin. Register 66-69 (Read-Only): DPLL Number Bits [31:0] Mnemonic dpll_num Default 32’d0 Bit Mnemonic Description [31:0] dpll_num Contains the ratio between the MCLK and the audio clock rate once the DPLL has acquired lock. This value is latched on reading the LSB, so register 66 must be read first to acquire the latest DPLL value. The value is latched on LSB because the DPLL number can be changing as the I2C transactions are performed. FSR = (dpll_num ∗ MCLK) 232 |
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