DRV8316 datasheet(49/97 Pages) TI

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8.3.15.1 VM Supply Undervoltage Lockout (NPOR)

If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold (VM UVLO falling

threshold), all of the integrated FETs, driver charge-pump and digital logic controller are disabled as shown in

Figure 8-40. Normal operation resumes (driver operation) when the VM undervoltage condition is removed. The

NPOR bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VM. The NPOR

bit remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST).

VUVLO (min) falling

VUVLO (max) falling

VUVLO (max) rising

VUVLO (min) rising

VVM

DEVICE ON

DEVICE OFF

DEVICE ON

Time

Figure 8-40. VM Supply Undervoltage Lockout

8.3.15.2 AVDD Undervoltage Lockout (AVDD_UV)

If at any time the voltage on AVDD pin falls lower than the VAVDD_UV threshold, all of the integrated FETs, driver

charge-pump and digital logic controller are disabled. Normal operation resumes (driver operation) when the

AVDD undervoltage condition is removed. The NPOR bit is reset and latched low in the IC status (IC_STAT)

CLR_FLT bit or an nSLEEP pin reset pulse (tRST).

8.3.15.3 BUCK Undervoltage Lockout (BUCK_UV)

If at any time the voltage on VFB_BK pin falls lower than the VBK_UV threshold, the integrated FETs of the buck

regulator are disabled while the driver FETs, charge pump, and digital logic control continue to operate normally.

The nFAULT pin is driven low in the event of a buck undervoltage fault, and the BK_FLT bit in IC_STAT register

is set in SPI devices. The FAULT and BUCK_UV bits are also latched high in the registers on SPI devices.

Normal operation starts again (buck regulator operation and the nFAULT pin is released) when the BUCK

undervoltage condition clears. The BK_FLT and BUCK_UV bits stay set until cleared through the CLR_FLT bit or

an nSLEEP pin reset pulse (tRST).

8.3.15.4 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold voltage of the

charge pump, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and VCP_UV

bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and

the nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set until cleared

through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST). The CPUV protection is always enabled in both

hardware and SPI device varaints.

8.3.15.5 Overvoltage Protections (OV)

If at any time input supply voltage on the VM pins rises higher lower than the VOVP threshold voltage, all of the

integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and OVP bits are also latched high

in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released)

when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin

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DRV8316-Q1

SLVSGK9 – JANUARY 2022

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