DRV8316 datasheet(24/97 Pages) TI

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8.3.3 Device Interface Modes

The DRV8316-Q1 family of devices supports two different interface modes (SPI and hardware) to let the end

application design for either flexibility or simplicity. The two interface modes share the same four pins, allowing

the different versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one

interface version and potentially switch to another with minimal modifications to their design.

8.3.3.1 Serial Peripheral Interface (SPI)

The SPI devices support a serial communication bus that lets an external controller send and receive data

with the DRV8316-Q1. This support lets the external controller configure device settings and read detailed

fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are

described as follows:

• The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on

the SDI and SDO pins.

• The SDI pin is the data input.

• The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup

resistor.

• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the

DRV8316-Q1.

For more information on the SPI, see the Section 8.5 section.

8.3.3.2 Hardware Interface

Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are GAIN,

SLEW, MODE, and OCP.

This conversion lets the application designer configure the most common device settings by tying the pin logic

high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for an SPI bus from

the external controller. General fault information can still be obtained through the nFAULT pin.

• The GAIN pin configures the gain of the current sense amplifier.

• The SLEW pin configures the slew rate of the output voltage.

• The MODE pin configures the PWM control mode.

• The OCP/SR pin is used to configures the OCP level and active demagnetization modes.

For more information on the hardware interface, see the Section 8.3.10 section.

SDI

SDO

SCLK

SPI

Interface

nSCS

VCC

AVDD

Figure 8-6. DRV8316R-Q1 SPI Interface

MODE

OCP/SR

SLEW

GAIN

SLEW

AVDD

Hardware

Interface

AVDD

Figure 8-7. DRV8316T-Q1 Hardware Interface

DRV8316-Q1

SLVSGK9 – JANUARY 2022

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