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4.8

SMBCTL (address 8014h): SMBus Control Register

SN8040

SN8045

Cool-GG Programmable Battery Management IC

SLUS753B – JANUARY 2007 – REVISED FEBRUARY 2008

This read-write register controls the operation of the SMBus peripheral.

SMBCTL REGISTER (ADDRESS 8014h)

Name

NC_SMB

BLI_EDGE

BLI_EN

PEC_DIS

BFI_EN

SMB_RST

ISOLATE

SA_EN

Access

R/W

Reset

NC_SMB (bit 7): SMBus high time timeout disable bit. This bit is used to disable the SMBus high time

timeout in systems that may not conform to SMBus specifications.

1 = SMBus high time timeout disabled

0 = SMBus high time timeout enabled, conforms to SMBus specifications

BLI_EDGE (bit 6): Bus low interrupt polarity bit. This bit determines whether to generate an interrupt

when BUS_LOW goes active, or when BUS_LOW goes inactive. BLI_EN must be set to

trigger a bus low interrupt. BLI_EDGE should only be set if BUS_LOW is already active.

1 = If BLI_EN=1, generates an interrupt when BUS_LOW goes inactive.

0 = If BLI_EN=1, generates an interrupt when BUS_LOW goes active.

BLI_EN (bit 5): Bus low interrupt enable bit. This bit is used to enable SMB bus low timeout detection, and

will generate an SMB interrupt if the SMBus clock and data lines have both been low for a

time exceeding the programmable SMB bus low timeout (SMBBUSLO register, default=2s).

This bit can be used to implement the charger broadcast re-enable function as described in

the Smart Battery Data specification.

1 = Enable SMB bus low detection.

0 = Disable SMB bus low detection.

PEC_DIS (bit 4): Packet error checking engine disable bit. This bit disables PEC engine to conserve

power if PEC checking or generation is not required.

1 = PEC engine disabled

0 = PEC engine enabled

BFI_EN (bit 3): Bus free interrupt enable bit. This bit enables interrupt when BUS_FREE is set.

1 = Assert interrupt in response to BUS_FREE assertion

0 = Mask assertion of interrupt in response to BUS_FREE assertion; BUS_FREE must be

polled to determine active state of SMBus

SMB_RST (bit 2): SMB engine software reset bit.

1 = Reset SMB engine

0 = SMB normal operation

ISOLATE (bit 1): SMBus isolation bit. This bit isolates SMB peripheral from SMBus.

1= Disconnect SMB peripheral from SMBus

0 = SMB normal operation

SA_EN (bit 0): Slave address detection enable bit. This bit enables assertion of SA_RDY to allow the

device to respond to multiple slave addresses.

1 = SA_RDY asserted in response to any slave address detected on SMBus; CPU required

to ACK or NACK address via SMBACK

0 = SMB normal operation; SMB engine ACKs address programmed in SMBTAR without

CPU intervention

System Management Bus (SMBus) Peripheral and Operation Interface

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