SN8045 datasheet(2/88 Pages) TI

2 / 88 page

Contents

SN8040

SN8045

Cool-GG Programmable Battery Management IC

SLUS753B – JANUARY 2007 – REVISED FEBRUARY 2008

Introduction

......................................................................................................................... 7

1.1

Features

....................................................................................................................... 7

1.2

Applications

................................................................................................................... 7

1.3

Description

.................................................................................................................... 7

1.4

Functional Block Diagram

.................................................................................................. 8

1.5

Terminal Assignments

....................................................................................................... 9

PACKAGE THERMAL DATA

............................................................................................. 10

Specifications

.................................................................................................................... 11

2.1

Absolute Maximum Ratings

............................................................................................... 11

2.2

Recommended Operating Conditions

................................................................................... 11

2.3

Electrical Characteristics

.................................................................................................. 12

2.4

Data Flash Characteristics Over Recommended Operating Temperature and Supply Voltage

................. 16

2.5

SMBus Timing Characteristics

............................................................................................ 16

2.5.1

Typical Characteristics

.................................................................................................... 18

General Operation Overview

................................................................................................ 19

3.1

Power Mode Control

....................................................................................................... 19

3.1.1

Power On Reset

................................................................................................. 19

3.1.2

Power Modes

.................................................................................................... 19

3.2

Watchdog Timer

............................................................................................................ 20

3.3

Cell Voltage Multiplexer and High Voltage Translation

................................................................ 20

3.3.1

2, 3 or 4 cell hardware configuration

.......................................................................... 20

3.3.2

Cell Voltage

...................................................................................................... 21

3.3.3

Battery Pack and Battery stack voltage

...................................................................... 21

3.4

Cell Balancing

.............................................................................................................. 21

3.5

Charge & Discharge N-Channel FET Drive

............................................................................. 21

3.6

Pre-Charge FET, GPOD Drive & 0V Charging

......................................................................... 21

3.7

AFE Control & Configuration

.............................................................................................. 22

3.8

Overload & Short Circuit Comparators & Delay

........................................................................ 22

3.9

CoolRISC Processor

....................................................................................................... 22

3.10

Data and Program Memory

............................................................................................... 23

3.11

Delta-Sigma ACD & integrating Coloumb Counter

.................................................................... 24

3.12

Internal Temperature Sensor

............................................................................................. 25

3.13

I/O Specialized Functions

................................................................................................. 25

3.14

Power Regulation & Management

....................................................................................... 25

3.15

Internal Oscillator

........................................................................................................... 25

3.16

Power Consumption

....................................................................................................... 26

3.17

Mask ROM Functions

...................................................................................................... 26

System Management Bus (SMBus) Peripheral and Operation Interface

..................................... 28

4.1

SMB Interrupts

.............................................................................................................. 28

4.2

Operating as a Slave

...................................................................................................... 28

4.2.1

For a Slave Read

................................................................................................ 28

4.2.2

For a Slave Write

................................................................................................ 29

4.3

Operating as a Master

..................................................................................................... 29

4.3.1

SMBMA Register for an LSB = 1: (R/W_B = 1), Master Read:

........................................... 29

4.3.2

SMBMA Register for an LSB = 0: (R/W_B = 0), Master Write:

............................................ 29

4.4

SMBMA (address 8010h):SMBus Master Address Register

......................................................... 30

4.5

SMBDA (address 8011h): SMBus Data Register

...................................................................... 30

4.6

SMBACK (address 8012h): SMBus Acknowledge Register

.......................................................... 30

4.7

SMBSTA (address 8013h): SMBus Status Register

................................................................... 31

4.8

SMBCTL (address 8014h): SMBus Control Register

.................................................................. 32

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