SN8045 datasheet(17/88 Pages) TI

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(LOW)

(HD:STA)

(SU:DAT)

(HIGH)

(HD:DAT)

(HD:STA)

(BUF)

SCLK

SDATA

(SU:STO)

SCLK

SDATA

Start

Stop

(LOW:SEXT)

(LOW:MEXT)

SCLK

ACK

(1)

SCLK

ACK

(1)

(SU:STA)

SN8040

SN8045

Cool-GG Programmable Battery Management IC

SLUS753B – JANUARY 2007 – REVISED FEBRUARY 2008

over operating free-air temperature range, Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t(HD:DAT)

Receive mode

Data hold time (see Figure 2-1)

Transmit mode

300

t(SU:DAT)

Data setup time (see Figure 2-1)

250

t(TIMEOUT)

Error signal/detect (see Figure 2-1)

See (1)

µs

t(LOW)

Clock low period (see Figure 2-1)

4.7

µs

t(HIGH)

Clock high period (see Figure 2-1)

See (2)

4.0

µs

t(LOW:SEXT)

Cumulative clock low slave extend time

See (3)

µs

t(LOW:MEXT) Cumulative clock low master extend time (see

See (4)

µs

Figure 2-1)

Clock/data fall time

See (5)

300

Clock/data rise time

See (6)

1000

(1)

The SN8040 times out when any clock low exceeds t(TIMEOUT).

(2)

t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 µs causes reset of any transaction involving SN8040 that is in

progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).

(3)

t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4)

t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.

(5)

Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)

(6)

Fall time tf = 0.9VDD to (VILMAX – 0.15)

SCLKACK is the acknowledge-related clock pulse generated by the master.

Figure 2-1. SMBus Timing Diagram

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Specifications

SN8045 Datasheet(PDF) 17 Page - Texas Instruments

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