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3.3.2

Cell Voltage

3.3.3

Battery Pack and Battery stack voltage

3.4

Cell Balancing

3.5

Charge & Discharge N-Channel FET Drive

3.6

Pre-Charge FET, GPOD Drive & 0V Charging

SN8040

SN8045

Cool-GG Programmable Battery Management IC

SLUS753B – JANUARY 2007 – REVISED FEBRUARY 2008

Table 3-2. 2, 3 or 4 cell hardware configuration

Cells

VC1

VC2

VC3

VC4

VC5

connect to VC3

top cell+

top cell- & bottom cell+

bottom cell-

middle cell - & bottom

connect to VC2

top cell+

top cell- & middle cell+

bottom cell-

cell+

top cell- & top medium

top medium cell- &

bottom medium cell- &

top cell+

bottom cell-

cell+

bottom medium cell+

bottom cell+

The individual cell voltages between VC5 VC4, VC4 VC3, VC3, VC2 and VC2 VC1 pins can be selected

with the CELL1, CELL0 bits in CELL_SEL register. The output of the voltage translation is presented to

RC0 and RC1 of the MCU RC register and can be read with the MCU ADC and also can be measured at

VCELL+ pin. The voltage output is inverse proportional to the VCx input using the following equation:

VCELL+ = –K × VCELLIN + 0.975V

Where:

• K = 0.150

• V

CELLIN = input voltage at VC(x) and VC(x+1) pin

The voltage at PACK pin and VC1 pin referenced to VSS pin can be selected with the BAT and PACK bit

in the FUNCTION_CTL register. If both bits are set at the same time, VC1 pin voltage is presented at the

output. The output of the voltage translation is presented to RC0 and RC1 of the MCU RC register and

can be read with the MCU ADC and also be measured at VCELL+ pin. The voltage output follows

following equation:

VCELL+ = VIN / 18

Where:

• V

IN = Voltage at PACK pin if PACK bit is set

• V

IN = Voltage at VC1 pin if BAT bit is set

The cell balancing allows a small controllable bypass path for the cells connected to the VCx pins. During

charging this bypass can reduce the charge current to any cell in the cell stack to adjust the cell charge to

the same level. The bypass current is set by series resistors placed between VCx pin and the cell. The

bypass can be selected in the CELL_SEL register of the AFE control.

The SN8040 has integrated charge pumps to drive the gates of charge and discharge N-FET. The charge

and discharge FET can be controlled with the OUTPUT_CONTROL register in the AFE control only if the

hardware protection not tripped. The SN8040 will turn either the CHG or DSG FET off if the hardware

overload or short-circuit protection trips. The default state of the CHG FET and DSG FET is off.

The SN8040/SN8045 can control a extra low current pre-charge path using P-FET with the ZVCHG pin in

addition to the charge FET. With the high voltage general purpose open drain output pin (GPOD)

additional control methods can be realized. both ZVCHG pin and GPOD pin can be controlled in the

OUTPUT_CONTROL register.

The device also supports current limited 0-V charging using CHG FET in case battery stack voltage is too

low for the device to operate. Connect PMS pin to PACK pin to enable 0V charging with the CHG FET.

Connect PMS pin to VSS to disable 0V charging with CHG FET.

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SN8045 Datasheet(PDF) 21 Page - Texas Instruments

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