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4.2.2

For a Slave Write

4.3

Operating as a Master

4.3.1

SMBMA Register for an LSB = 1: (R/W_B = 1), Master Read:

4.3.2

SMBMA Register for an LSB = 0: (R/W_B = 0), Master Write:

SN8040

SN8045

Cool-GG Programmable Battery Management IC

SLUS753B – JANUARY 2007 – REVISED FEBRUARY 2008

transmitted byte is checked by reading the NACKED bit. Ordinarily the final data byte is NACKed by the

master, indicating the master is finished receiving data. If the expected final data byte is ACKed by the

master, this indicates a PEC byte is to be sent. In this case, the PEC_SND bit in the SMBPEC register

(8014h) is set in response to D_REQ. This setting clears D_REQ and instructs the SMB peripheral to send

a PEC byte; SMBDA should not be written. In response to the final D_REQ with NACKED = 1, the CPU

should write a 0 to SMBACK to clear D_REQ.

The SMB peripheral is receiving data sent from the master. After each byte of received data, D_RDY is

asserted, signaling the CPU that the data byte is ready to be read from SMBDA. The CPU needs to ACK

or NACK the byte by writing to the SMBACK register, clearing D_RDY. If a data byte is to be checked as a

PEC byte, the PEC_VLD bit in the SMBPEC register is checked after assertion of the final D_RDY and

before writing the final ACK (or NACK).

The CPU must first verify that the SMBus is not currently active. Verification is by either polling the

BUS_FREE bit in the SMBSTA register or setting the BFI_EN bit in the SMBCTL register. Once the bus is

verified inactive, the CPU may then write the address of the slave device it wishes to communicate with to

the SMBMA register. If the transaction is a read from the slave, the LSB of this register is written as a 1.

Otherwise, if the transaction is a write to the slave, the LSB is written as a 0.

After transmitting the slave address, the SMB peripheral asserts a D_REQ. Then, successful

acknowledgment of the address by the slave is indicated by the bit NACKED = 0. If NACKED = 1, the

CPU may abort the transaction by writing a 0 to SMBACK. This action clears D_REQ and a stop condition

is sent to free the bus. Otherwise, with NACKED = 0, the transaction is continued with the CPU writing the

required SMBus command to SMBDA. This clears D_REQ and instruct the SMB peripheral to send the

contents of SMBDA on the SMBus. D_REQ is asserted again after the command has been ACKed or

NACKed by the slave. If ACKed, the next step is dependent on the LSB of SMBMA.

D_REQ is cleared by writing a 1 to SMBACK, causing the SMB peripheral to send a repeated start

followed by the repeated SLAVE address with its LSB = 1. This repeated address is ACKed or NACKed

by the slave, and is verified by reading the NACKed bit after the next assertion of D_REQ. The D_REQ is

cleared by writing a 1 to SMBACK. Then data are sent to the SMB peripheral from the slave device. After

each byte of received data, D_RDY is asserted signaling the CPU that the data bit is ready to be read

from SMBDA. The CPU then ACKs or NACKs the byte by writing to SMBACK, clearing D_RDY. If a data

byte is to be checked as a PEC byte, the PEC_VLD bit is checked after assertion of the final D_RDY and

before writing the final NACK. The final data byte to be read, or the PEC byte, is NACKed, which signals

the SMB to end the master read and send a stop.

D_REQ signals the request for data to be sent to the slave and is cleared by writing the requested data to

the SMBDA register. Upon each assertion of D_REQ, the status of the slave’s ACK or NACK of the

preceding byte is checked by reading the NACKED bit. If a PEC byte is to be sent, PEC_SND is set in

response to the D_REQ preceding the byte to be considered a PEC byte. Writing to PEC_SND clears

D_REQ; the SMBDA register should not be written. If no more data are to be sent, the CPU should write a

0 to the SMBACK register in response to the final D_REQ, which clears D_REQ and sends a stop.

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