TUSB1104 datasheet(37/55 Pages) TI

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Table 7-19. SS_EQ Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

SSEQ1_SEL

RH/W

This field selects EQ for USB SSTX1 receiver which faces the USB

host. When EQ_OVERRIDE = 0b, this field reflects the sampled

state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can

change the EQ setting for SSTX1p/n pins based on value written to

this field.

7.6.1.10 USB3_MISC Register (Offset = 22h) [Reset = 04h]

USB3_MISC is shown in Table 7-20.

Return to the Summary Table.

Table 7-20. USB3_MISC Register Field Descriptions

Bit

Field

Type

Reset

Description

RXD_START_TERM

R/W

Termination setting at start of RX detection following warm reset and

at entry to SS.Inactive.

0h = Maintain termination.

1h = Turn off termination. Avoid compliance failures due to race

between local and remote rxd in case of disconnect. If connection

remains next state was polling regardless.

6-5

U23_RXDET_INTERVAL

R/W

This field controls the Rx.Detect interval for the downstream facing

port (CTX1P/N and CTX2P/N) when in U2/U3.

0h = 48ms

1h = 84ms

2h = 120ms

3h = 156ms

DISABLE_U2U3_RXDET

R/W

Controls whether or not Rx.Detect is performed in U2/U3 state.

0h = Rx.Detect in U2/U3 enabled.

1h = Rx.Detect in U2/U3 disabled.

3-2

DFP_RXDET_INTERVAL

R/W

This field controls the Rx.Detect interval for the downstream facing

port (CTX1P/N and CTX2P/N).

0h = 4ms

1h = 6ms

2h = 36ms

3h = 84ms

DIS_WARM_RESET_RXD R/W

Disables receiver detection following warm reset if device starts

polling during warm reset.

0h = whether receiver detection is done following warm reset

depends on other settings.

1h = if USB FSM detects that device started polling during warm

reset, it will not do receiver detection.

USB_COMPLIANCE_CTR

R/W

Controls whether compliance mode detection is determined by FSM

or disabled

0h = Compliance mode determined by FSM.

1h = Compliance mode disabled.

7.6.1.11 USB1_STATUS Register (Offset = 24h) [Reset = 01h]

USB1_STATUS is shown in Table 7-21.

Return to the Summary Table.

Table 7-21. USB1_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

USB1_FASTAEQ_STAT

When AEQ_EN = 1 and AEQ_MODE = x0, this status field indicates

whether short or long EQ setting is used. When AEQ_EN = 0, this

field will always default to 0h.

0h = Short channel EQ used.

1h = Long channel EQ used.

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TUSB1104

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