TUSB1104 datasheet(24/55 Pages) TI

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7.3.5 USB Polarity Inversion

The USB 3.2 standard requires all host, hubs, and devices support USB polarity inversion detection and

correction. For this reason, polarity between TUSB1104 and USB connector as well as between USB Host/

Device and TUSB1104 does not have to be maintained. Not maintaining polarity will simplify layout by

eliminating the need to swap P and N in the layout. The Figure 7-1 shows example in which polarity between

USB host and redriver is not maintained.

USB 3.2

Host/Device

redriver

SSTXp

SSTXn

SSRXp

SSRXn

SSTXn

SSTXp

SSRXn

SSRXp

CTXp

CTXn

CRXp

CRXn

TXp

TXn

RXp

RXn

Polarity inverted

Figure 7-1. Polarity Inversion Example

7.3.6 Receiver Detect Control

The SLP_S0# pin offers system designers the ability to control the TUSB1104 Rx.Detect functionality during

Disconnect and U2/U3 states and therefore achieving lower consumption in these states. When the system is

in a low power state (Sx where x = 1, 2, 3, 4, or 5), system can assert SLP_S0# low to disable TUSB1104

receiver detect functionality. While SLP_S0# is asserted low and USB 3.2 interface is in U3, the TUSB1104

keeps receiver termination active. The TUSB1104 will not respond to any LFPS signaling while in this state.

This means that system wake from U3 is not supported while SLP_S0# is asserted low. If the TUSB1104 is

in Disconnect state when SLP_S0# is asserted low, then TUSB1104 disables all channels receiver termination

and disables receiver detect functionality. When SLP_S0# is asserted high, the TUSB1104 resumes normal

operation of performing far-end receiver termination detection.

Note

As there is a single SLP_S0# pin, this pin when asserted low impact both port 1 (CRX1, CTX1,

SSRX1, SSTX1) and port 2 (CRX2, CTX2, SSRX2, SSTX2).

7.4 Device Functional Modes

7.4.1 MODE Pin

The MODE pin selects between between I2C mode and pin-strap mode. Refer to Table 7-5 for details.

In I2C mode, the TUSB1104 supports either 1.8-V LVCMOS or 3.3-V LVCMOS signalling based on the sampled

state of VIO_SEL pin.

Table 7-5. MODE pin Function

MODE pin level

Description

Reserved.

Reserved

I2C Mode

Pin-strap mode.

TUSB1104

SLLSFL1 – APRIL 2022

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