TUSB1104 datasheet(45/55 Pages) TI

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12 Application Curves

Figure 12-1. 10 Gbps Input Eye At SSTX1

After 12.5 dB at 5 GHz Pre-channel

Figure 12-2. 10 Gbps Output Eye at CTX1

After 1.2 dB at 5 GHz Post-Channel

13 Power Supply Recommendations

The TUSB1104 is designed to operate with a 3.3 V power supply. Levels above those listed in the Absolute

Maximum Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator

can be used to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power

supply integrity. A 0.1 μF de-coupling capacitor should be used on each power pin. The de-coupling capacitor

should be placed close as possible to the power pin. It is also recommended to have a single bulk capacitor of 1

μF to 10 μF.

14 Layout

14.1 Layout Guidelines

1. SSTX1P/N, SSRX1P/N, SSTX2P/N, SSRX2P/N, CRX1P/N, CRX2PN, CTX1P/N, and CTX2P/N pairs should

be routed with controlled 90-Ω differential impedance (±10%).

2. Keep away from other high speed signals.

3. Intra-pair routing (between P and N) should be kept to less than 5 mils.

4. Length matching should be near the location of mismatch.

5. Each pair should be separated at least by 3 times the signal trace width.

6. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of

left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This

will minimize any length mismatch caused by the bends and therefore minimize the impact bends have on

EMI.

7. Route all differential pairs on the same of layer.

8. The number of vias should be kept to a minimum. It is recommended to keep the vias count to 2 or less.

9. Keep traces on layers adjacent to ground plane.

10. Do not route differential pairs over any plane split.

11. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance.

If test points are used, they should be placed in series and symmetrically. They must not be placed in a

manner that causes a stub on the differential pair.

12. Highly recommended to have reference plane void under USB-C receptacle's super speed pins to minimize

the capacitance effect of the receptacle.

13. Highly recommended to have reference plane void under the AC-coupling capacitances.

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TUSB1104 Datasheet(PDF) 45 Page - Texas Instruments