SAF7741 datasheet(24/83 Pages) NXP

24 / 83 page

SAF7741_5

Objective data sheet

Rev. 05 — 09 May 2008

24 of 83

NXP Semiconductors

SAF7741HV

Dual IF car radio and audio DSP (N1F)

the data remains valid while the clock is high. After 16 falling and 16 rising edges the

whole buffer is read out and the bits are stored by the microprocessor. After a 17th falling

clock edge the data line is set high until the other 16-bit buffer is full. The microprocessor

stops communication by pulling the clock line high again. See Section 14.1.

7.1.5.5

RDS demodulator

The RDS demodulator is implemented in DSP software. See Ref. 1 for details of its

functionality.

Demodulator decoder interface: Communication between the RDS demodulator and

decoder is provided by Economic Parameterized Integrated Cores (EPICS) flags and

consists of four signals as shown in Figure 15.

Remark: Instead of the EPICS flags, the RDS decoder connection register can be used

for demodulator decoder communication. For further details see Ref. 3.

Remark: The current version of the SAF7741HV firmware does not use bslp/bspa

signalling. This is implemented in the hardware, and is therefore mentioned here for

information only.

7.1.6 8Fs I2S interface

The 8Fs I2S interface is used to transform the parallel data outputs of the TDSP1 (24 bits

wide) to serial data in I2S format, and then make that data available at the digital radio

interface 1 (see Figure 16). The TDSP1 has the capability to write data to the interface at

1Fs, 2Fs, 4Fs and 8Fs.

Depending on the flag values, the interface can send data in I2S format at 1Fs, 2Fs, 4Fs,

8Fs and 16Fs.

Table 10.

Signals provided by the demodulator

Name

Description

rdcl

Demodulator clock output.

Generated by the RDS/RBDS demodulator for every RDS/RBDS clock period

(1.1875 kHz). This pulse remains high for about half of an RDS/RBDS clock

period (

∼420 μs). The rising edge of this signal is used as an input shift enable for

the decoder internal data buffer (RDS Data Output [RDDA] bit input).

It is assumed that the RDDA input will remain unchanged for at least one system

clock (10.4 MHz) after a rising RDCL edge.

rdda

Demodulator data output.

Represents the actual RDS/RBDS data bit. The RDDA is shifted into the decoder

module internal data buffer by detection of a rising edge on the RDCL input

signal.

bslp

Bit-Slip (BSLP) detected.

This is set to high for at least one RDS/RBDS clock period (1.1875 kHz), but only

when the demodulator detects a possible BSLP. The BSLP signal itself has to be

reset to low after one RDS/RBDS clock period.

Table 11.

Signals received by the demodulator

Name

Description

bspa

Bit-Slip Process Active (BSPA).

This is set to HIGH when the RDS decoder detects a BSLP: at all other times it is

LOW.

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