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SAF7741 Datasheet(PDF) 12 Page - NXP Semiconductors |
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SAF7741 Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 83 page ![]() SAF7741_5 © NXP B.V. 2008. All rights reserved. Objective data sheet Rev. 05 — 09 May 2008 12 of 83 NXP Semiconductors SAF7741HV Dual IF car radio and audio DSP (N1F) • Dual tuner, which offers antenna, phased-array or MPX diversity • Single tuner on the smallest possible hardware set: preferably one DSP 7.1.1 IFADCs For each tuner path two fully differential ΣΔ IFADCs are used for the I and Q paths. For each IFADC two fully differential input nodes are fed with a 300 kHz input signal. This design provides good suppression of even harmonics. The noise is shaped by a 5th order loop filter to get sufficient resolution in the band of interest, and for complex filtering the input signal of the I and Q paths has a 90 ° phase shift. The IFADCs are sampled by a 41.6 MHz clock. The output is a 1-bit bitstream signal with a frequency of 41.6 MHz (see Figure 4). 7.1.1.1 TEF6730 tuner compatibility mode In this mode the IF input signal is 10.7 MHz differential. The mixer is in front of the IFADC, and this converts the input signal down to 300 kHz using a quadrature 10.4 MHz square wave. The 300 kHz down-converted signal is then fed to the IFADCs as I and Q signals. Switching to TEF6730 tuner compatibility mode is performed via the I2C interface and is only available to the microprocessor. 7.1.2 Primary decimation chain The PDC (see Figure 5) decimates the incoming sample rate from the IFADC, shifts the signal to baseband and applies Amplitude Gain Control (AGC) step compensation, linear AGC correction and IQ Correction (IQC). Fig 4. Simplified block diagram of an IFADC 10.4 MHz 41.6 MHz IFADINPP IFADINPP MIXER Gm LOOP FILTER QUANTIZER VOUT DAC 41.6 MHz RDAC RDAC Rin Rin |
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