SAF7741 datasheet(34/83 Pages) NXP

34 / 83 page

SAF7741_5

Objective data sheet

Rev. 05 — 09 May 2008

34 of 83

NXP Semiconductors

SAF7741HV

Dual IF car radio and audio DSP (N1F)

7.2.4 Audio ADC decimator paths (DAD)

7.2.4.1

Functional description

Decimation of the audio ADC signals is completed in a block called DAD. This block can

handle the signals from two ADCs, so a stereo signal can be processed.

The input signal has a sample frequency of 128

× fs and comes from a third-order ΣΔ

ADC. The first step in the decimation process is done by the 1-bit code Cascaded

Integrator Comb (CIC) filter and Audio Decimation Filter 1 (ADF1) filter. See Figure 26.

The CIC filter decimates the input sample rate by a factor of 16 and thus results in a

sample rate of 8

× fs.

After the 1-bit code filter, sample reworking is necessary to enter the CEAD block and the

ADF2. The CEAD block further decimates the audio samples by 8, giving a sample rate of

× fs. The overall gain in the pass band of the decimation filter (including the CIC filter

and the CEAD block) becomes 4.85 dB. A nominal input level of

−8.45 dB comes from the

ADC and results in a

−3.6 dB level after decimation.

Fig 25. Single-ended input

PHONE

NEGATIVE

220nF

8.2 k

22uF

AIN3

AIN3_REF

VREFAD

ADX

anselX

gndselX

dif_swX

10 k

1nF

Fig 26. DAD block diagram

CEAD

BLOCK

CEAD

INTERFACE

1 Bit CODE

FILTER

CONTROL

Enable DC FILTER

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