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SAF7741 Datasheet(PDF) 28 Page - NXP Semiconductors

Part # SAF7741
Description  Dual IF car radio and audio DSP
PDF  83 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SAF7741 Datasheet(HTML) 28 Page - NXP Semiconductors

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SAF7741_5
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 05 — 09 May 2008
28 of 83
NXP Semiconductors
SAF7741HV
Dual IF car radio and audio DSP (N1F)
corresponding pins is switched off. Which RDS decoder is connected to which TDSP is
controlled in the I2C registers. Table 13 shows which flags are used for RDS when
connected.
7.1.9.1
EPICS flag generator
The EPICS flag generator generates two flags: IFLAG and the Sync Flag (SFLAG). IFLAG
is connected to the ‘I’ input flag of the EPICS and SFLAG is connected to the user flag 0.
SFLAG indicates that the EPICS should use page0 of the EPICS interface memories to
avoid read and/or write errors and conflicts.
The normal duration of IFLAG is four EPICS clock periods. The SFLAG is set until the
next IFLAG is generated.
The EPICS can stretch (IMODE) IFLAG via the IM input.
7.1.9.2
Flag overview
When IFLAG is in stretch mode (IM is high) the flag is set at every rising edge of LFLAG.
IFLAG can be reset only with the RESET_I input connected to a DIO address. When this
address is read by the EPICS, RESET_I is pulsed. SFLAG is not stretched. If IFLAG is not
cleared before the next LFLAG the LOST_DATA flag is set.
When IFLAG is not in stretch mode (IM is low) then an IFLAG is generated at every rising
edge of the LFLAG . If at this point PFLAG is high, then SFLAG is set until the next rising
edge of LFLAG (see Figure 19). LFLAG and PFLAG are generated in the software radio
flag generator.
Remark: F11 and F12 are not available outside of the chip.
Fig 18. Overview of RDS user-defined flag configuration
F1
F12
F2 F3 F4 F5 F6 F7 F8 F9 F10F11
TDSP1
F1
F12
F2 F3 F4 F5 F6 F7 F8 F9 F10F11
TDSP2
F1
F12
F2 F3 F4 F5 F6 F7 F8 F9 F10F11
TDSP1E
TDSP_IO F1
RDS1
RDS1
RDS2
RDS2
RDS1
RDS2
&
F1_ mode (tdsp1e)
&
F1_ mode (tdsp2)
&
F1_ mode (tdsp1)
F1_ mode (tdsp1)
F1_ mode (tdsp2)
F1_ mode (tdsp1e)
(Outpu t is ena b
led when one ou t of three mod es is ou tpu t)



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