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AD5941 Datasheet(PDF) 62 Page - Analog Devices

Part # AD5941
Description  High Precision, Impedance, and Electrochemical Front End
PDF  134 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5941 Datasheet(HTML) 62 Page - Analog Devices

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AD5940/AD5941
Data Sheet
Rev. C | Page 62 of 134
Bits
Bit Name
Settings
Description
Reset
Access
011000
VBIAS0 – Measured at VBIAS pin
011001
Voltage on CE0 pin, VCE0.
011010
Voltage on RE0 pin, VRE0.
011011
AFE4
011100
Reserved.
011101
AFE1.
011110
AFE2.
011111
VCE0/2.
100000
Reserved.
100001
Low power TIA positive output, LPTIA_P.
100010
Reserved.
100011
AGND_REF.
100100
Positive node of excitation amplifier.
Repeat ADC Conversions Control Register—REPEATADCCNV
Address 0x000021F0, Reset: 0x00000160, Name: REPEATADCCNV
Table 52. Bit Descriptions for REPEATADCCNV Register
Bits
Bit Name
Settings
Description
Reset
Access
[31:12]
Reserved
Reserved.
0x0
R
[11:4]
NUM
Repeat value. Writing 0 to these bits causes unpredictable operation.
0x16
R/W
1
1 conversion.
0xFF
256 conversions.
[3:1]
Reserved
Reserved.
0x0
R
0
EN_P enable
Enable repeat ADC conversions.
0x0
R/W
0
Disable repeat ADC conversions.
1
Enable repeat ADC conversions.
ADC Buffer Configuration Register—ADCBUFCON
Address 0x0000238C, Reset: 0x005F3D00, Name: ADCBUFCON
The recommended value is 0x005F3D0F in high power mode and 0x005F3D04 in low power mode.
Table 53. Bit Descriptions for ADCBUFCON
Bits
Bit Name
Settings
Description
Reset
Access
[31:9]
Reserved
Reserved.
0x0
R
[8:4]
AMPDIS
Set these bits to 1 to disable the op amp. Set these bits to 0 to enable the op amp.
0x10
R/W
Bit 8 controls the offset cancellation buffers.
Bit 7 controls the ADC buffers.
Bit 6 controls the PGA.
Bit 5 controls the positive front-end buffer.
Bit 4 controls the negative front-end buffer.
[3:0]
CHOPDIS
Set these bits to 1 to disable chop. Set these bits to 0 to enable chop. Clear these
bits when measuring signals <80 kHz. Set these bits when measuring signals >80 kHz.
0x0
R/W
Bit 3 controls the offset cancellation buffers.
Bit 2 controls the ADC buffers.
Bit 1 controls the PGA.
Bit 0 controls the front-end buffers.



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