AD5941 datasheet(16/134 Pages) AD

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AD5940/AD5941

Data Sheet

Rev. C | Page 16 of 134

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Low Power Reference

1.65

µA

Low Power DACs for VZERO0 and

VBIAS0

2.3

µA

Low power DAC powered up, excluding load

current

Low Power TIA and

Potentiostat Amplifier

µA

Per amplifier, normal mode

µA

Per amplifier, half power mode

START-UP TIME

Processor clock = 16 MHz

AFE Wake-Up2

Wake-up time to allow communication on SPI

bus

ADC Wake-Up2

180

µs

Time delay required on exiting hibernate mode

before starting ADC conversions

VBIAS_CAP is only meant for internal biasing within the IC.

Guaranteed by design, not production tested.

Code distribution can be reduced if ADC output rate is reduced by using sinc2 filter option.

ADC offset and gain not calibrated for high power mode in production. User calibration can eliminate this error.

There is a correction factor of 1.835 V introduced to the ADC code to voltage conversion as a result of the calibration to the ADC.

A 1.835 V/1.82 V factor must be added while performing the calibration.

The 1.82 V reference is used to calibrate the ADC offset and gain.

If the ADC is calibrated and there is a hardware reset, the calibration registers are cleared to the default value. One way around this clear is to store the calibrated

values in the MCU flash during factory calibration and load those values on power-up.

Noise can be reduced if ADC sample rate is reduced using the sinc2 filter. See Table 2 for ADC rms noise: digital filter settings.

The low power TIA gain resistor must be calibrated regularly because the resistor has a high temperature drift.

See Figure 8 for details.

See Figure 10 for details.

VBIAS0 can be used for sourcing the offset voltage to external amplifiers.

High speed DAC offset calibration can remove this error. See the High Speed DAC Calibration Options section for details.

Measured using the box method.

The watchdog can be turned off during system initialization.

IOVDD can optionally be powered from a 1.8 V supply rail.

ADC RMS NOISE SPECIFICATIONS

The internal 1.82 V reference is used for all measurements.

ADC RMS Noise: Digital Filter Settings

Table 2 provides the rms noise specifications for the ADC with different ADC digital filter settings.

Table 2. ADC RMS Noise1

Update

Rate (Hz)

Sinc3 Oversampling

Rate (OSR)

Sinc2 OSR

Gain = 1 rms

Noise (μV)

Gain = 1.5 rms

Noise (μV)

Gain = 2 rms

Noise (μV)

Gain = 4 rms

Noise (μV)

Gain = 9 rms

Noise (μV)

200,000

Not applicable

72.43

49.732

37.83

18.93

8.62

9090

29.29

19.59

10.4

6.687

4.42

900

178

24.0

17.11

12.832

6.416

1.018

Noise can be reduced if ADC sample rate is reduced using the sinc2 filter.

ADC RMS Noise: Peak-to-Peak Effective Bits

Table 3 provides the rms and peak-to-peak effective bits based on the noise results in Table 2 for various PGA gain settings (peak-to-peak

effective bits results are shown in parentheses). To calculate the rms bits, use the following equation:

log2 ((2 × Input Range)/RMS Noise)

where:

Input Range is the input voltage range to the ADC.

RMS Noise is the rms of the noise.

To calculate the peak-to-peak effective bits, use the following equation:

log2 ((2 × Input Range)/(6.6 × RMS Noise))

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