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AD5941 Datasheet(PDF) 65 Page - Analog Devices |
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AD5941 Datasheet(HTML) 65 Page - Analog Devices |
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65 / 134 page ![]() Data Sheet AD5940/AD5941 Rev. C | Page 65 of 134 ADC Offset Calibration Auxiliary Channel (PGA Gain = 1) Register—ADCOFFSETGN1 Address 0x00002244, Reset: 0x00000000, Name: ADCOFFSETGN1 Table 60. Bit Descriptions for ADCOFFSETGN1 Register Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. 0x0 R [14:0] Value Offset calibration gain = 1. ADC offset correction for the auxiliary channel with PGA gain = 1, represented as a twos complement number. The calibration resolution is 0.25 LSBs of the ADCDAT LSB size. Therefore, the calibration resolution is ±VREF/218. If VREF = 1.82 V, the calibration resolution is 1.82/217 = 13.885 µV. 0x0 R/W 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum negative offset calibration value. 0x4000 −4096. Maximum negative offset calibration value. ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 1) Register—ADCGAINGN1 Address 0x00002240, Reset: 0x00004000, Name: ADCGAINGN1 The ADCGAINGN1 register provides gain calibration for the voltage input channels to the ADC, including the AINx channels. Table 61. Bit Descriptions for ADCGAINGN1 Register Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. 0x0 R [14:0] Value Gain calibration for PGA gain = 1. ADC gain correction for auxiliary input channels. These bits are used for all channels, except the TIA and temperature sensor channels when PGA gain = 1. This value is stored as a signed number. Bit 14 is the sign bit, and Bits[13:0] represent the fractional part. 0x4000 R/W 0x0000 0. Illegal value; results in an ADC result of 0x8000. 0x2000 0.5. ADC result multiplied by 0.5. 0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default). 0x4001 1.000061. Minimum positive gain adjustment. 0x7FFF 2. Maximum positive gain adjustment. 0x0001 0.000061. Maximum negative gain adjustment. 0x3FFF 0.999939. Minimum negative gain adjustment. ADC Offset Calibration Auxiliary Input Channel (PGA Gain = 1.5) Register—ADCOFFSETGN1P5 Address 0x000022CC, Reset: 0x00000000, Name: ADCOFFSETGN1P5 The ADCOFFSETGN1P5 register provides ADC input offset calibration with PGA gain =1.5. Table 62. Bit Descriptions for ADCOFFSETGN1P5 Register Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. 0x0 R [14:0] Value Offset calibration gain = 1.5. ADC offset correction with PGA gain = 1.5. 0x0 R/W 0x3FFF 4095.75. Maximum positive offset calibration value. 0x0001 0.25. Minimum positive offset calibration value. 0x0000 0. No offset adjustment. 0x7FFF −0.25. Minimum negative offset calibration value. 0x4000 −4096. Maximum negative offset calibration value. |
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