HT46R53 datasheet(6/42 Pages) HOLTEK

6 / 42 page

HT46R53/HT46R54

Rev. 1.40

July 12, 2005

Functional Description

Execution Flow

The system clock for the microcontroller is derived from

either a crystal or an RC oscillator. The system clock is

internally divided into four non-overlapping clocks. One

instruction cycle consists of 4 system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch and decoding takes an instruction cy-

cle while execution take the next instruction cycle. The

pipelining scheme causes each instruction to effectively

execute in a cycle. If an instruction changes the program

counter, two cycles are required to complete the instruc-

tion.

Program Counter

- PC

For HT46R53, the program counter (PC) is 11 bits wide

and controls the sequence in which the instructions

stored in the program ROM are executed. The contents

of the PC can specify a maximum of 2048 addresses.

For HT46R54, the program counter (PC) is 12 bits wide

and controls the sequence in which the instructions

stored in the program ROM are executed. The contents

of the PC can specify a maximum of 4096 addresses.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points to

the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex-

ecution, loading register, subroutine call or return from

subroutine, initial reset, internal interrupt, external inter-

rupt or return from interrupts, the PC manipulates the

program transfer by loading the address corresponding

to each instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get the proper instruction.

Otherwise proceed to the next instruction.

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

S y s t e m C l o c k

O S C 2 ( R C o n l y )

P C

Execution Flow

Mode

Program Counter

*b11 *b10

*b9

*b8

*b7

*b6

*b5

*b4

*b3

*b2

*b1

*b0

Initial Reset

000000000000

External Interrupt

000000000100

Timer/Event Counter Overflow

000000001000

A/D Converter Interrupt

000000001100

Skip

Program Counter+2

Loading PCL

PC11 PC10 PC9

PC8

Jump, Call Branch

#11

#10

Return from Subroutine

S11

S10

Program Counter

Note:

*b11~*b0: Program counter bits

S11~S0: Stack register bits

#11~#0: Instruction code bits

@7~@0: PCL bits, PC11~PC8: Original PC counter, remain unchanged

For the HT46R53, the program counter is 11 bits wide (b0~b10), the b11 column in the table are not applicable.

For the HT46R54, the program counter is 12 bits wide, i.e. from b0~b11.

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