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SI3232 Datasheet(PDF) 13 Page - Silicon Laboratories |
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SI3232 Datasheet(HTML) 13 Page - Silicon Laboratories |
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13 / 128 page  Si3232 Preliminary Rev. 0.96 13 Figure 1. SPI Timing Diagram Table 10. Switching Characteristics—SPI (VDD, VDD1–VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF) Parameter Symbol Test Conditions Min Typ Max Unit Cycle Time SCLK tc 0.062 — — µs Rise Time, SCLK tr — — 25 ns Fall Time, SCLK tf — — 25 ns Delay Time, SCLK Fall to SDO Transition td2 — — 20 ns Delay Time, CS Rise to SDO Tristate td3 — — 20 ns Setup Time, CS to SCLK Rise tsu1 15 — — ns Hold Time, SCLK Rise to CS Rise th1 20 — — ns Setup Time, SDI to SCLK Rise tsu2 25 — — ns Hold Time, SCLK Rise to SDI Rise th2 20 — — ns SDI to SDITHRU Propagation Delay — 6 — ns Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VDD –0.4 V, VIL = 0.4 V SCLK CS SDI t h1 t d3 SDO t d2 t su1 t r t r t c t su2 t h2 |
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