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LTM4650 Datasheet(PDF) 20 Page - Analog Devices

Part # LTM4650
Description  Source/Sink Dual ±25A or Single ±50A μModule Regulator with Input Overvoltage Protection
PDF  38 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4650 Datasheet(HTML) 20 Page - Analog Devices

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LTM4652
20
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK pin of the
slave regulator, as shown in Figure 9.
Following Equation 7, the ratio of the master’s output
slew rate (MR) to the slave’s output slew rate (SR) is
determined by Equation 8.
MR
SR
=
RFB(SL)
RFB(SL)+60.4k
RTR(BOT)
RTR(TOP)+RTR(BOT)
(8)
For example, VOUT(MA)=1.5V, MR = 1.5V/1ms and VOUT(SL)
= 3.3V, SR = 3.3V/1ms. From Equation 8, we could solve
that RTR(TOP) = 60.4k and RTR(BOT) = 40.2k are a good
combination for the ratiometric tracking.
The TRACK pin will have the 1.25µA current source on
when a resistive divider is used to implement tracking
on the slave regulator. This will impose an offset on
the TRACK pin input. Smaller value resistors with the
same ratios as the resistor values calculated from the
Equation 8 can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
Coincident output tracking can be recognized as a special
ratiometric output tracking in which the master’s output
slew rate (MR) is the same as the slave’s output slew rate
(SR), waveform as shown in Figure 10.
From Equation 8, we could easily find that, in coinci-
dent tracking, the slave regulator’s TRACK pin resistor
divider is always the same as its feedback divider given
by Equation 9.
RFB(SL)
RFB(SL)+60.4k
=
RTR(BOT)
RTR(TOP)+RTR(BOT)
(9)
Figure 9. Example of Output Tracking Application Circuit
4652 F09
LTM4652
VIN
VINOVP
RUN1
RUN2
TEMP+
TEMP–
TRACK1
TRACK2
fSET
C8
470µF
6.3V
RFB(SL)
13.3k
R2
10k
C6
100µF
6.3V
×3
PHASMD
VOUT1
VOUTS1
SW1
VFB1
VFB2
COMP1
COMP2
VOUTS2
VOUT2
SW2
PGOOD2
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
PGOOD1
INTVCC
SGND
GND
VOUT1
(MASTER)
1.5V
RAMP TIME
tSOFTSTART = (CSS/1.25µA) • 0.6V
DIFFP
DIFFN DIFFOUT
40.2k
10k
4.7nF
PGOOD2
SLAVE
VOUT1
(MASTER)
1.5V
±25A
C7
470µF
6.3V
C5
100µF
6.3V
×3
10k
3.3nF
R4
140k
RTR(TOP)
60.4k
4.5V TO 18V INTERMEDIATE BUS
R6
845k
CSS
C1
22µF
25V
RTR(BOT)
40.2k
C2
22µF
25V
C3
22µF
25V
C4
22µF
25V
C10
4.7µF
R9
10k
INTVCC
VOUT2
(SLAVE)
3.3V
±25A



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