LTM4650 datasheet(24/38 Pages) AD

24 / 38 page

LTM4652

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

As a practical matter, it should be clear to the reader

that no individual or sub-group of the four thermal resis-

tance parameters defined by JESD51-12 or provided in

the Pin Configuration section replicates or conveys nor-

mal operating conditions of a µModule. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bottom

of the µModule—as the standard defines for θJCtop and

θJCbot, respectively. In practice, power loss is thermally

dissipated in both directions away from the package—

granted, in the absence of a heat sink and airflow, a major-

ity of the heat flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-9 to predict power loss heat flow and temperature

readings at different interfaces that enable the calculation

of the JEDEC-defined thermal resistance values; (3) the

model and FEA software is used to evaluate the µMod-

ule with heat sink and airflow; (4) having solved for and

analyzed these thermal resistance values and simulated

various operating conditions in the software model, a

thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled-envi-

ronment chamber while operating the device at the same

power loss as that which was simulated. The outcome

of this process and due diligence yields the set of derat-

ing curves provided in later sections of this data sheet,

along with well-correlated JESD51-12-defined θ values

provided in the Pin Configuration section of this data

sheet. Each system has its own thermal characteristics,

therefore thermal analysis must be performed by the user

in a particular system.

The LTM4652 module has been designed to effectively

remove heat from both the top and bottom of the pack-

age. The bottom substrate material has very low thermal

resistance to the printed circuit board. An external heat

sink can be applied to the top of the device for excellent

heat sinking with airflow.

Figure 13 shows the thermal image of the LTM4652,

without airflow, without heat sink, running paralleled

from 12V to 1V at 50A with around 85.3% efficiency and

8.6W power loss. Figure 14 shows the thermal image of

the LTM4652, with 200LFM airflow, without heat sink,

running paralleled from 12V to 3.3V at 50A with around

92.2% efficiency and 14W power loss.

Figure 12. Graphical Representation of JESD51-12 Thermal Coefficients

4652 F12

µModule DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

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