MPC8540 datasheet(581/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-77

Figure 13-62. Effect of LUPWAIT Signal

13.4.4.5

Synchronous Sampling of LUPWAIT for Early Transfer

Acknowledge

If LUPWAIT is to be considered an asynchronous signal, which can be asserted/negated at any

time, no UPM RAM word must contain both WAEN = 1 and UTA = 1 simultaneously.

However, programming WAEN = 1 and UTA = 1 in the same RAM word allows UPM to treat

LUPWAIT as a synchronous signal, which must meet set-up and hold times in relation to the rising

edge of the bus clock. In this case, as soon as UPM samples LUPWAIT negated on the rising edge

of the bus clock, it immediately generates an internal transfer acknowledge, which allows a data

transfer one bus clock cycle later. The generation of transfer acknowledge is early because

LUPWAIT is not re-synchronized, and the acknowledge occurs regardless of whether UPM was

already frozen in WAIT cycles or not. This feature allows the synchronous negation of LUPWAIT

to affect a data transfer, even if UTA, WAEN, and LAST are set simultaneously.

13.4.4.6

Extended Hold Time on Read Accesses

Slow memory devices that take a long time to turn off their data bus drivers on read accesses

should choose some non-zero combination of ORn[TRLX] and ORn[EHTR]. The next accesses

after a read access to the slow memory device is delayed by the number of clock cycles specified

in the ORn register in addition to any existing bus turn around cycle.

LCSn

LGPL1

WAEN

Word n

Word n+1

LUPWAIT

c9 c10 c11

c12

c13 c14

Word n+2

Wait

Word n+3

LCLK

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