MPC8540 datasheet(579/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-75

Note that any change to the AMX field from one RAM word to the next RAM word executed

results in an address phase on the LAD[0:31] bus with the assertion of LALE for the number of

cycles set for LALE in the ORn and LCRR registers. The LGPL[0:5] signals maintain the value

specified in the RAM word during the LALE phase.

13.4.4.4.8 Data Valid and Data Sample Control (UTA)

When a read access is handled by the UPM, and the UTA bit is 1 (data is to be sampled by the

LBC), the value of the DLT3 bit in the same RAM word, in conjunction with MxMR[GPLn4DIS],

determines when the data input is sampled by the LBC as follows:

•

If MxMR[GPLn4DIS] = 1 (G4T4/DLT3 functions as DLT3) and DLT3 = 1 in the RAM

word, data is latched on the falling edge of the bus clock instead of the rising edge. The LBC

samples the data on the next falling edge of the bus clock, which is during the middle of the

current bus cycle. This feature should be used only in systems without external

synchronous bus devices that require mid-cycle sampling.

•

If GPLn4DIS = 0 (G4T4/DLT3 functions as G4T4), or if GPLn4DIS = 1 but DLT3 = 0, data

is latched on the rising edge of the bus clock, which occurs at the end of the current bus

clock cycle (normal operation).

Table 13-32. UPM Address Multiplexing

LAD[0:31]

as Address

Signals

A0–A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

000 Signal

driven on

external pin

when

address

multiplexing

is enabled—

RAM word

AMX = 10

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23

001

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

010

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

011

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20

100

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

101

A10 A11 A12 A13 A14 A15 A16 A17 A18

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