MPC8540 datasheet(576/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-72

Freescale Semiconductor

Local Bus Controller

13.4.4.4.2 Chip-Select Signal Timing (CSTn)

If BRn[MSEL] of the accessed bank selects a UPM on the currently requested cycle, the UPM

manipulates the LCSn for that bank with timing as specified in the UPM RAM word CSTn fields.

The selected UPM affects only the assertion and negation of the appropriate LCSn signal. The

state of the selected LCSn signal of the corresponding bank depends on the value of each CSTn

bit. Figure 13-59 shows how UPMs control LCSn signals.

Figure 13-59. LCSn Signal Selection

13.4.4.4.3 Byte Select Signal Timing (BSTn)

If BRn[MSEL] of the accessed memory bank selects a UPM on the currently requested cycle, the

selected UPM affects the assertion and negation of the appropriate LBS[0:3] signal. The timing of

all four byte-select signals is specified in the RAM word. However, LBS[0:3] are also controlled

by the port size of the accessed bank, the number of bytes to transfer, and the address accessed.

Figure 13-60 shows how UPMs control LBS[0:3].

UPMA/B/C

SDRAM

GPCM

MUX

BRn[MSEL]

LCS3

LCS4

LCS5

LCS6

LCS7

Switch

Bank Selected

LCS0

LCS1

LCS2

MPC8540 Datasheet(PDF) 576 Page - Freescale Semiconductor, Inc