MPC8540 datasheet(575/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-71

EXEN

Exception enable. Allows branching to an exception pattern at the exception start address (EXS).

When an internal bus monitor time-out exception is recognized and EXEN in the RAM word is set,

the UPM branches to the special exception start address (EXS) and begins operating as the pattern

defined there specifies.

The user should provide an exception pattern to negate signals controlled by the UPM in a

controlled fashion. For DRAM control, a handler should negate RAS and CAS to prevent data

corruption. If EXEN = 0, exceptions are ignored by UPM (but not by Local Bus) and execution

continues. After the UPM branches to the exception start address, it continues reading until the

LAST bit is set in the RAM word.

0 The UPM continues executing the remaining RAM words, ignoring any internal bus monitor

time-out.

1 The current RAM word allows a branch to the exception pattern after the current cycle if an

exception condition is detected.

26–27

AMX

Address multiplexing. Determines the source of LAD[0:31] during a LALE phase. Any change in the

AMX field initiates a new LALE (address) phase.

00 LAD[0:31] is the non-multiplexed address. For example, column address.

01 Reserved

10 LAD[0:31] is the address multiplexed according to MxMR[AM]. For example, row address.

11 LAD[0:31] is the contents of MAR. Used, for example, to initialize a mode.

Note that Source ID debug mode is only supported for the AMX = 00 setting.

Next burst address. Determines when the address is incremented during a burst access.

0 The address increment function is disabled.

1 The address is incremented in the next cycle. In conjunction with the BRn[PS], the increment

value of the state of LA[27:31] is 1, 2 or 4 for port sizes of 8-bits, 16-bits and 32-bits, respectively.

UTA

UPM transfer acknowledge. Indicates assertion of transfer acknowledge in the current cycle.

0 Transfer acknowledge is not asserted in the current cycle.

1 Transfer acknowledge is asserted in the current cycle.

TODT

Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to be

guaranteed between two successive accesses to the same memory bank. This feature is critical

when DRAM requires a RAS precharge time. TODT turns the timer on to prevent another UPM

access to the same bank until the timer expires.The disable timer period is determined in

MxMR[DSn]. The disable timer does not affect memory accesses to different banks. Note that TODT

must be set together with LAST, otherwise it is ignored.

0 The disable timer is turned off.

1 The disable timer for the current bank is activated preventing a new access to the same bank

(when controlled by the UPMs) until the disable timer expires. For example, precharge time.

LAST

Last word. When LAST is read in a RAM word, the current UPM pattern terminates and control

signal timing set in the RAM word is applied to the current (and last) cycle. However, if the disable

timer is activated and the next access is to the same bank, execution of the next UPM pattern is held

off and the control signal values specified in the last word are extended in duration for the number

of clock cycles specified in MxMR[DSn].

0 The UPM continues executing RAM words.

1 Indicates the last RAM word in the program. The service to the UPM request is done after this

cycle concludes.

Table 13-30. RAM Word Field Descriptions (continued)

Bits

Name

Description

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