MPC8540 datasheet(571/1302 Pages) FREESCALE

Part #	MPC8540

Description	MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual

PDF	1302 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-67

The division of UPM bus cycles into phases is shown in Figure 13-55 and Figure 13-56. If

LCRR[CLKDIV] = 2, the bus cycle comprises only two active phases, T1 and T3, which

correspond with the first and second halves of the bus clock cycle, respectively. However, if

LCRR[CLKDIV] = 4 or 8, four phases, T1–T4, define four quarters of the bus clock cycle.

Because T2 and T4 are inactive when LCRR[CLKDIV] = 2, UPM ignores signal timing

programmed for assertion in either of these phases in the case LCRR[CLKDIV] = 2.

Figure 13-55. UPM Clock Scheme for LCRR[CLKDIV] = 2

Figure 13-56. UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8

13.4.4.4

RAM Array

The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure 13-57.

The signals at the bottom of the figure are UPM outputs. The selected LCSn is for the bank that

matches the current address. The selected LBS is for the byte lanes read or written by the access.

LCLK

MPC8540 Datasheet(PDF) 571 Page - Freescale Semiconductor, Inc