MPC8540 datasheet(567/1302 Pages) FREESCALE

567 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-63

The following events initiate a UPM cycle:

•

Any internal device requests an external memory access to an address space mapped to a

chip-select serviced by the UPM

•

A UPM refresh timer expires and requests a transaction, such as a DRAM refresh

•

A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an

exception sequence

The RAM array contains 64 words of 32-bits each. The signal timing generator loads the RAM

word from the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the

UPM reads a RAM word with WAEN set, the external LUPWAIT signal is sampled and

synchronized by the memory controller and the current request is frozen.

13.4.4.1

UPM Requests

A special pattern location in the RAM array is associated with each of the possible UPM requests.

An internal device’s request for a memory access initiates one of the following patterns

(MxMR[OP] = 00):

•

Read single-beat pattern (RSS)

•

Read burst cycle pattern (RBS)

•

Write single-beat pattern (WSS)

•

Write burst cycle pattern (WBS)

A UPM refresh timer request pattern initiates a refresh timer pattern (RTS).

An exception (caused by a bus monitor time-out error) occurring while another UPM pattern is

running initiates an exception condition pattern (EXS).

Figure 13-53 and Table 13-29 show the start addresses of these patterns in the UPM RAM,

according to cycle type. RUN commands (MxMR[OP] = 11), however, can initiate patterns

starting at any of the 64 UPM RAM words.

MPC8540 Datasheet(PDF) 567 Page - Freescale Semiconductor, Inc