MPC8540 datasheet(569/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-65

Any transfers that do not naturally fit single or burst transfers are synthesized as a series of single

transfers. These accesses are treated by the UPM as back-to-back, single-beat transfers. Burst

transfers can also be inhibited by setting ORn[BI]. Burst performance can be achieved by ensuring

that UPM transactions are 32-byte aligned with a transaction size being some multiple of 32-bytes,

which is a natural fit for cache-line transfers, for example.

13.4.4.1.2 UPM Refresh Timer Requests

Each UPM contains a refresh timer that can be programmed to generate refresh service requests

of a particular pattern in the RAM array. Figure 13-54 shows the clock division hardware

associated with memory refresh timer request generation. The UPM refresh timer register (LURT)

defines the period for the timers associated with all three UPMs.

Figure 13-54. Memory Refresh Timer Request Block Diagram

By default, all local bus refreshes are performed using the refresh pattern of UPMA. This means

that if refresh is required, MAMR[RFEN] must be set. It also means that only one refresh routine

should be programmed and be placed in UPMA, which serves as the refresh executor. Any banks

assigned to a UPM are provided with the refresh pattern if the RFEN bit of the corresponding UPM

is set. UPMA assigned banks, therefore, always receive refresh services when MAMR[RFEN] is

set, while UPMB and UPMC assigned banks also receive (the same) refresh services if the

corresponding MxMR[RFEN] bits are set.

Note that the UPM refresh timer request should not be used in a system with SDRAM refresh

enabled. The system designer must choose to use either SDRAM refresh or UPM refresh. Using

both may result in missing refresh periods to memory.

13.4.4.1.3 Software Requests—RUN Command

Software can start a request to the UPM by issuing a RUN command to the UPM. Some memory

devices have their own signal handshaking protocol to put them into special modes, such as

self-refresh mode. Other memory devices require special commands to be issued on their control

signals, such as for SDRAM initialization.

For these special cycles, the user creates a special RAM pattern that can be stored in any unused

areas in the UPM RAM. Then a RUN command is used to run the cycle. The UPM runs the pattern

beginning at the specified RAM location until it encounters a RAM word with its LAST bit set.

The RUN command is issued by setting MxMR[OP] = 11 and accessing UPMn memory region

with any write transaction that hits the corresponding UPM machine. MxMR[MAD] determines

the starting address in the RAM array for the pattern.

UPM refresh timer request

System

Divide by LURT

PTP Prescaling

Clock

MPC8540 Datasheet(PDF) 569 Page - Freescale Semiconductor, Inc