MPC8540 datasheet(570/1302 Pages) FREESCALE

570 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-66

Freescale Semiconductor

Local Bus Controller

Note that transfer acknowledges (UTA bit in the RAM word) are ignored for software (RUN

command) requests, and hence the LAD signals remain high-impedance unless the normal initial

LALE occurs or the RUN pattern causes assertion of LALE to occur on changes to the RAM word

AMX field.

13.4.4.1.4 Exception Requests

When the LBC under UPM control initiates an access to a memory device and an exception occurs

(bus monitor time-out), the UPM provides a mechanism by which memory control signals can

meet the device’s timing requirements without losing data. The mechanism is the exception pattern

that defines how the UPM negates its signals in a controlled manner.

13.4.4.2

Programming the UPMs

The UPM is a micro sequencer that requires microinstructions or RAM words to generate signal

timings for different memory cycles. Follow these steps to program UPMs:

1. Set up BRn and ORn registers.

2. Write patterns into the RAM array.

3. Program MRTPR, LURT and MAMR[RFEN] if refresh is required.

4. Program MxMR.

Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM with

any write transaction that hits the relevant chip select. The entire array is thus programmed by an

alternating series of writes: to MDR (RAM word to be written) each time followed by a (dummy)

write transaction to the relevant UPM assigned bank.

Note that the UPM memory region must be cache-inhibited or write-through (the MMU page must

have the I or W bit set) during the time that the UPM array is being written. If the memory is to be

cacheable and/or copyback, the MMU must be set accordingly after the UPM array is initialized.

RAM array contents may also be read for debug purposes, for example, by alternating dummy read

transactions, each time followed by reads of MDR (when MxMR[OP] = 10).

13.4.4.3

UPM Signal Timing

RAM word fields specify the value of the various external signals at a granularity of up to four

values for each bus clock cycle. The signal timing generator causes external signals to behave

according to timing specified in the current RAM word. For LCRR[CLKDIV] = 4 or 8, each bit

in the RAM word relating to LCSn and LBS timing specifies the value of the corresponding

external signal at each quarter phase of the bus clock. If LCRR[CLKDIV] = 2, the external signal

can change value only on each half phase of the bus clock. If the RAM word in this case

(LCRR[CLKDIV] = 2) specifies a quarter phase signal change, the signal timing generator

interprets this as a half cycle change.

MPC8540 Datasheet(PDF) 570 Page - Freescale Semiconductor, Inc