MPC8540 datasheet(573/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-69

Table 13-30 describes RAM word fields.

Table 13-30. RAM Word Field Descriptions

Bits

Name

Description

CST1

Chip select timing 1. Defines the state (0 or 1) of LCSn during bus clock quarter phase 1 if

LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCSn during bus clock half phase 1 if

LCRR[CLKDIV] = 2.

CST2

Chip select timing 2. Defines the state (0 or 1) of LCSn during bus clock quarter phase 2 if

LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.

CST3

Chip select timing 3. Defines the state (0 or 1) of LCSn during bus clock quarter phase 3 if

LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCSn during bus clock half phase 2 if

LCRR[CLKDIV] = 2.

CST4

Chip select timing 4. Defines the state (0 or 1) of LCSn during bus clock quarter phase 4.if

LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.

BST1

Byte select timing 1. Defines the state (0 or 1) of LBS during bus clock quarter phase 1

(LCRR[CLKDIV] = 4 or 8) or bus clock half phase 1 (LCRR[CLKDIV] = 2), in conjunction with

BRn[PS] and the state of LA[30:31].

BST2

Byte select timing 2:. Defines the state (0 or 1) of LBS during bus clock quarter phase 2

(LCRR[CLKDIV] = 4 or 8), in conjunction with BRn[PS] and the state of LA[30:31]. Ignored when

LCRR[CLKDIV] = 2.

BST3

Byte select timing 3. Defines the state (0 or 1) of LBS during bus clock quarter phase 3

(LCRR[CLKDIV] = 4 or 8) or bus clock half phase 2 (LCRR[CLKDIV] = 2), in conjunction with

BRn[PS] and the state of LA[30:31].

BST4

Byte select timing 4. Defines the state (0 or 1) of LBS during bus clock quarter phase 4

(LCRR[CLKDIV] = 4 or 8), in conjunction with BRn[PS] and the state of LA[30:31]. Ignored when

LCRR[CLKDIV] = 2.

8–9

G0L

General-purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases 1 and

2 (first half phase).

00 Value defined by MxMR[G0CL]

01 Reserved

10 0

11 1

10–11

G0H

General-purpose line 0 higher. Defines the state of LGPL0 during the bus clock quarter phases 3

and 4 (second half phase).

00 Value defined by MxMR[G0CL]

01 Reserved

10 0

11 1

G1T1

General-purpose line 1 timing 1. Defines the state (0 or 1) of LGPL1 during bus clock quarter phases

1 and 2 (first half phase).

G1T3

General-purpose line 1 timing 3. Defines the state (0 or 1) of LGPL1 during bus clock quarter phases

3 and 4 (second half phase)

G2T1

General-purpose line 2 timing 1. Defines state (0 or 1) of LGPL2 during bus clock quarter phases 1

and 2 (first half phase).

G2T3

General-purpose line 2 timing 3. Defines the state (0 or 1) of LGPL2 during bus clock quarter phases

3 and 4 (second half phase).

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