MPC8540 datasheet(574/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-70

Freescale Semiconductor

Local Bus Controller

G3T1

General-purpose line 3 timing 1. Defines the state (0 or 1) of LGPL3 during bus clock quarter phases

1 and 2 (first half phase).

G3T3

General-purpose line 3 timing 3. Defines the state (0 or 1) of LGPL3 during bus clock quarter phases

3 and 4 (second half phase).

G4T1/DLT3

General-purpose line 4 timing 1/delay time 3. The function of this bit is determined by MxMR[GPL4].

If MxMR[GPL4] = 0 and LGPL4/LUPWAIT pin functions as an output (LGPL4), G4T1/DLT3 defines

the state (0 or 1) of LGPL4 during bus clock quarter phases 1 and 2 (first half phase).

If MxMR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), if a read burst or single

read is executed, G4T1/DLT3 defines the sampling of the data bus as follows:

0 In the current word, the data bus should be sampled at the start of bus clock quarter phase 1 of

the next bus clock cycle.

1 In the current word, the data bus should be sampled at the start of bus clock quarter phase 3 of

the current bus clock cycle.

G4T3/WAEN General-purpose line 4 timing 3/wait enable. Bit function is determined by MxMR[GPL4].

If MxMR[GPL4] = 0 and LGPL4/LUPWAIT pin functions as an output (LGPL4), G4T3/WAEN defines

the state (0 or 1) of LGPL4 during bus clock quarter phases 3 and 4 (second half phase).

If MxMR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), G4T3/WAEN is used

to enable the wait mechanism:

0 LUPWAIT detection is disabled.

1 LUPWAIT is enabled. If LUPWAIT is detected as being asserted, a freeze in the external signals

logical values occurs until LUPWAIT is detected as being negated.

G5T1

General-purpose line 5 timing 1. Defines the state (0 or 1) of LGPL5 during bus clock quarter phases

1 and 2 (first half phase).

G5T3

General-purpose line 5 timing 3. Defines the state (0 or 1) of LGPL5 during bus clock quarter phases

3 and 4 (second half phase).

22–23

REDO

Redo current RAM word. Defines the number of times to execute the current RAM word.

00 Once (normal operation)

01 Twice

10 Three times

11 Four times

LOOP

Loop start/end. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop

start word. The next RAM word where LOOP is 1 is the loop end word. RAM words between, and

including the start and end words, are defined as part of the loop. The number of times the UPM

executes this loop is defined in the corresponding loop fields of the MxMR.

0 The current RAM word is not the loop start word or loop end word.

1 The current RAM word is the start or end of a loop.

Table 13-30. RAM Word Field Descriptions (continued)

Bits

Name

Description

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