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MPC8540 Datasheet(PDF) 578 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 578 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
13-74
Freescale Semiconductor
Local Bus Controller
loop end word. Loops can be executed sequentially but cannot be nested. Also, special care must
be taken if LAST and LOOP must not be set together.
13.4.4.4.6 Repeat Execution of Current RAM Word (REDO)
The REDO function is useful for wait-state insertion in a long UPM routine that would otherwise
need too many RAM words. Setting the REDO bits of the RAM word to a nonzero value causes
the UPM to re-execute the current RAM word up to three more times, as defined in the REDO field
of the current RAM word.
Special care must be taken in the following cases:
•
When UTA and REDO are set together, TA is asserted the number of times specified by the
REDO function.
•
When NA and REDO are set together, the address is incremented the number of times
specified by the REDO function.
•
When LOOP and REDO are set together, the loop mechanism works as usual and the line
is repeated according to the REDO function.
•
LAST and REDO must not be set together.
•
REDO should not be used within the exception routine.
13.4.4.4.7 Address Multiplexing (AMX)
The address lines can be controlled by the pattern the user provides in the UPM. The address
multiplex bits can choose between driving the transaction address, driving it according to the
multiplexing specified by the MxMR[AM] field, or driving the MAR contents on the address
signals. In all cases, LA[27:31] of the LBC are driven by the five lsbs of the address selected by
AMX, regardless of whether the NA bit of the RAM word is used to increment the current address.
The effect of NA = 1 is visible only when AMX = 00 chooses the column address.
Table 13-32 shows how MxMR[AM] settings affect address multiplexing when the RAM word
AMX = 10. The 16 msbs of the LAD[0:31] bus during an address phase are driven with zero in
the AMX = 10 case.
Table 13-31. MxMR Loop Field Use
Request Serviced
Loop Field
Read single-beat cycle
RLF
Read burst cycle
RLF
Write single-beat cycle
WLF
Write burst cycle
WLF
Refresh timer expired
TLF
RUN command
RLF



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