MPC8540 datasheet(580/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-76

Freescale Semiconductor

Local Bus Controller

Figure 13-61 shows how data sampling is controlled by the UPM.

Figure 13-61. UPM Read Access Data Sampling

13.4.4.4.9 LGPL[0:5] Signal Negation (LAST)

When the LAST bit is read in a RAM word, the current UPM pattern is terminated at the end of

the current cycle. On the next cycle (following LAST) all the UPM signals are negated

unconditionally (driven to logic 1), unless there is a back-to-back UPM request pending. In this

case, the signal values for the cycle following the one in which the LAST bit was set are taken

from the first RAM word of the pending UPM routine.

13.4.4.4.10Wait Mechanism (WAEN)

The WAEN bit in the RAM array word can be used to enable the UPM wait mechanism in selected

UPM RAM words. If the UPM reads a RAM word with WAEN set, the external LUPWAIT signal

is sampled and synchronized by the memory controller as if it were an asynchronous signal. The

WAEN bit is ignored if LAST = 1 in the same RAM word.

Synchronization of LUPWAIT starts at the rising edge of the bus clock and takes at least 1 bus

cycle to complete. If LUPWAIT is asserted and WAEN = 1 in the current UPM word, the UPM is

frozen until LUPWAIT is negated. The value of external signals driven by the UPM remains as

indicated in the previous RAM word. When LUPWAIT is negated, the UPM continues normal

functions. Note that during WAIT cycles, the UPM does not handle data.

Figure 13-62 shows how the WAEN bit in the word read by the UPM and the LUPWAIT signal

are used to hold the UPM in a particular state until LUPWAIT is negated. As the example shows,

the LCSn and LGPL1 states and the WAEN value are frozen until LUPWAIT is recognized as

negated. WAEN is typically set before the line that contains UTA = 1. Note that if WAEN and NA

are both set in the same RAM word, NA causes the burst address to increment once as normal

regardless of whether the UPM freezes.

To internal

data bus

LCLK

UPM read AND GPL4nDIS = 1 AND DLT3 = 1

LAD[0:31]

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