MPC8540 datasheet(577/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-73

Figure 13-60. LBS Signal Selection

The uppermost byte select (LBS0), when asserted, indicates that LAD[0:7] contains valid data

during a cycle. Likewise, LBS1 indicates that LAD[8:15] contains valid data, LBS2 indicates that

LAD[16:23] contains valid data, and LBS3 indicates that LAD[24:31] contains valid data. For a

UPM refresh timer request, all LBS[0:3] signals are asserted/negated by the UPM according to the

refresh pattern only. Following any internal bus monitor exception, LBS[0:3] signals are negated

regardless of the exception handling provided by any UPM exception pattern to prevent spurious

writes to external RAM.

13.4.4.4.4 General-Purpose Signals (GnTn, GOn)

The general-purpose signals (LGPL[0:5]) each have two bits in the RAM word that define the

logical value of the signal to be changed at the rising edge of the bus clock and/or at the falling

edge of the bus clock. LGPL0 offers enhancements beyond the other LGPLn lines.

GPL0 can be controlled by an address line specified in MxMR[G0CL]. To use this feature, G0H

and G0L should be set in the RAM word. For example, for a SIMM with multiple banks, this

address line can be used to switch between internal memory device banks.

13.4.4.4.5 Loop Control (LOOP)

The LOOP bit in the RAM word specifies the beginning and end of a set of UPM RAM words that

are to be repeated. The first time LOOP = 1, the memory controller recognizes it as a loop start

word and loads the memory loop counter with the corresponding contents of the loop field shown

in Table 13-31. The next RAM word for which LOOP = 1 is recognized as a loop end word. When

it is reached, the loop counter is decremented by one.

Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM

word executed is the loop start word. Otherwise, the next RAM word executed is the one after the

UPMA

MUX

BRn[MSEL]

LBS0

LBS1

LBS2

LBS3

Bank Selected

BRn[PS]

A[29:31]

Byte count

Byte-Select

Logic

UPMB

UPMC

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