MPC8540 datasheet(572/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-68

Freescale Semiconductor

Local Bus Controller

Figure 13-57. RAM Array and Signal Generation

13.4.4.4.1 RAM Words

The RAM word is a 32-bit microinstruction stored in one of 64 locations in the RAM array. It

specifies timing for external signals controlled by the UPM. Figure 13-58 shows the RAM word

fields. When LCRR[CLKDIV] = 4 or 8, the CSTn and BSTn bits determine the state of UPM

signals LCSn and LBS[0:3] at each quarter phase of the bus clock. When LCRR[CLKDIV] = 2,

CST2 and CST4 are ignored and the external has the values defined by CST1 and CST3 but

extended to half the clock cycle in duration. The same interpretation occurs for the BSTn bits when

LCRR[CLKDIV] = 2.

CST1 CST2 CST3

CST4 BST1 BST2 BST3 BST4

G0L

G0H

G1T1 G1T3 G2T1 G2T3

Reset

0000_0000_0000_0000

G3T1 G3T3

G4T1/

DLT3

G4T3/

WAEN

G5T1 G5T3

REDO

LOOP EXEN

AMX

UTA TODT LAST

Reset

0000_0000_0000_0000

Offset

Figure 13-58. RAM Word Field Descriptions

T1, T2, T3, T4

LGPL0

LGPL2 LGPL3 LGPL4 LGPL5

External Signals Timing Generator

RAM Array

CS Line

Selector

Byte Select

Logic

LCS[0:7]

LBS[0:3]

Current Bank

BRn[PS], LA[30,31]

32 Bits

64 deep

LGPL1

Clock Phases

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