MPC8540 datasheet(568/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-64

Freescale Semiconductor

Local Bus Controller

Figure 13-53. RAM Array Indexing

13.4.4.1.1 Memory Access Requests

The user must ensure that the UPM is appropriately initialized before a request occurs.

The UPM supports two types of memory reads and writes:

•

A single-beat transfer transfers one operand consisting of up to a single word (dependent

on port size). A single-beat cycle starts with one transfer start and ends with one transfer

acknowledge.

•

A burst transfer transfers exactly 4 double words regardless of port size. For 32-bit

accesses, the burst cycle starts with one transfer start but ends after eight transfer

acknowledges, whereas an 8-bit device requires 32 transfer acknowledges.

The user must ensure that patterns for single-beat transfers contain one, and only one, transfer

acknowledge (UTA bit in RAM word set high) and for a burst transfer, contain the exact number

of transfer acknowledges required.

Table 13-29. UPM Routines Start Addresses

UPM Routine

Routine Start Address

Read single-beat (RSS)

0x00

Read burst (RBS)

0x08

Write single-beat (WSS)

0x18

Write burst (WBS)

0x20

Refresh timer (RTS)

0x30

Exception condition (EXS)

0x3C

Write Single-Beat Request

Read Burst Request

Read Single-Beat Request

Write Burst Request

RAM Array

Refresh Timer Request

Exception Condition Request

RSS

RBS

WSS

WBS

RTS

EXS

64 RAM

Words

Array Index

Generator

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