MPC8540 datasheet(565/1302 Pages) FREESCALE

565 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-61

Figure 13-50. SDRAM MODE-SET Command

13.4.3.11 SDRAM Refresh

The memory controller supplies AUTO-REFRESH commands to any connected SDRAM device

according to the interval specified in LSRT (and prescaled by MRTPR[PTP]). This represents the

time period required between refreshes. The values of LSRT and MRTPR depend on the specific

SDRAM devices used and the system clock frequency of the LBC. This value should allow for a

potential collision between memory accesses and refresh cycles. The period of the refresh interval

must be greater than the access time to ensure that read and write operations complete successfully.

There are two levels of refresh request priority—low and high. The low priority request is

generated as soon as the refresh timer expires; this request is granted only if no other requests to

the memory controller are pending. If the request is not granted (memory controller is busy) and

the refresh timer expires two more times, the request becomes high priority and is served when the

current memory controller operation finishes.

13.4.3.11.1 SDRAM Refresh Timing

The SDRAM memory controller implements bank staggering for the auto refresh function. This

reduces instantaneous current consumption for memory refresh operations.

After a refresh request is granted, the memory controller begins issuing an AUTO-REFRESH

command to each device associated with the refresh timer. After a refresh command is issued to

an SDRAM device, the memory controller waits for the number of bus clock cycles programmed

in the SDRAM machine’s mode register (LSDMR[RFCR]) before issuing any subsequent

ACTIVATE command to the same device. To avoid violating SDRAM device timing constraints,

the user should ensure that the refresh request interval, defined by LSRT and MRTPR, is greater

than the refresh recovery interval, defined by LSDMR[RFCR].

1111

ZZZZZZZZ MODE

ZZZZZZZZ

LCLK

LALE

LCSn

LSDRAS

LSDCAS

LSDWE

LSDDQM[0:3]

LAD[0:31]

MODE-SET

Command

MPC8540 Datasheet(PDF) 565 Page - Freescale Semiconductor, Inc