MPC8540 datasheet(561/1302 Pages) FREESCALE

561 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-57

Figure 13-38. WRC = 2 (2 Clock Cycles)

13.4.3.7.5 Refresh Recovery Interval (RFRC)

This parameter, controlled by LSDMR[RFRC], defines the earliest timing for an ACTIVATE or

REFRESH command after a REFRESH command to the same SDRAM device.

Figure 13-39. RFRC = 4 (6 Clock Cycles)

13.4.3.7.6 External Address and Command Buffers (BUFCMD)

If the additional delay of any buffers placed on the command strobes (LSDRAS, LSDCAS,

LSDWE and LSDA10), is endangering the device setup time, LSDMR[BUFCMD] should be set.

Setting this bit causes the memory controller to add LCRR[BUFCMDC] extra bus cycles to the

assertion of SDRAM control signals (LSDRAS, LSDCAS, LSDWE and LSDA10) for each

SDRAM command.

1111

0000

1111

ZZZZZZZZ

CAS ADD

RAS ADD

CAS ADD

LCLK

LALE

LCSn

LSDRAS

LSDCAS

LSDWE

LSDDQM[0:3]

LAD[0:31]

0000

WRC = 2

Last Data In

PRECHARGE

Command

WRITE

Command

1111

ZZZZZZZZ

RAS ADD

XXXX

CAS ADD

LCLK

LALE

LCSn

LSDRAS

LSDCAS

LSDWE

LSDDQM[0:3]

LAD[0:31]

RFRC = 4 (6 clocks)

AUTO REFRESH

Command

ACTIVATE

Command

PRECHARGE ALL

Command (if needed)

PRETOACT = 3

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