MPC8540 datasheet(558/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-54

Freescale Semiconductor

Local Bus Controller

the address to the page register each time a bus-cycle access is requested. If a match is found,

together with a bank match, the bus cycle is defined as a page hit. An open page is automatically

closed by the SDRAM machine if the bus becomes idle, unless ORn[PMSEL] = 1.

13.4.3.5

Page Management

The LBC can manage at most four open pages (one page per SDRAM bank) for a single SDRAM

device. After a page is opened, it remains open unless:

•

The next access is to a page in a different SDRAM device, in which case all open pages on

the current device are closed with a PRECHARGE-ALL-BANKS command.

•

The next access is to a page in an SDRAM bank that has a different page open on it, in

which case the old page is closed with a PRECHARGE-SINGLE-BANK command.

•

The current SDRAM device requires refresh services, in which case all open pages on the

current device are closed with a PRECHARGE-ALL-BANKS command.

•

The bus becomes idle and ORn[PMSEL] = 0, in which case all open pages in the current

device are closed with a PRECHARGE-ALL-BANKS command.

13.4.3.6

SDRAM Address Multiplexing

The lower address bus bits are connected to the memory device’s address port with the memory

controller multiplexing the row/column and the internal bank select lines. The position of the bank

select lines are set according to LSDMR[BSMA]. Figure 13-34 shows how the SDRAM controller

shifts the row address down to the lower output address signals during activate and shifts the bank

select bits up to the address pins specified by LSDMR[BSMA], supporting page-based

interleaving. The lsb of the logical row address (An in Figure 13-34) is aligned with the connected

lsb of LAD (bits 29, 30, and 31 for port sizes of 32, 16, and 8 bits, respectively).

Figure 13-34. SDRAM Address Multiplexing

ROW

COLUMN

Activate Address (RAS):

msbs

lsbs

ROW

lsbs

To memory

device pins,

031

Logical Address:

lsbs

ROW

COLUMN

R/W Address (CAS):

—

except A10

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